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Fix CI badge 

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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Kainan Cha 2021-10-20 17:20:47 +08:00
parent 300850a8fa
commit 2243afcb6e
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.github/workflows/cmake_x86_vsim_unit_test.yml vendored
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name: x86_vsim_unit_test name: cmake_x86_vsim_unit_test
on: on:
# push: # push:

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README.md
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# TIM-VX - Tensor Interface Module # TIM-VX - Tensor Interface Module
![VSim.X86.UnitTest](https://github.com/VeriSilicon/TIM-VX/actions/workflows/x86_vsim_unit_test.yml/badge.svg) ![Bazel.VSim.X86.UnitTest](https://github.com/VeriSilicon/TIM-VX/actions/workflows/bazel_x86_vsim_unit_test.yml/badge.svg)
![CMake.VSim.X86.UnitTest](https://github.com/VeriSilicon/TIM-VX/actions/workflows/cmake_x86_vsim_unit_test.yml/badge.svg)
TIM-VX is a software integration module provided by VeriSilicon to facilitate deployment of Neural-Networks on Verisilicon ML accelerators. It serves as the backend binding for runtime frameworks such as Android NN, Tensorflow-Lite, MLIR, TVM and more. TIM-VX is a software integration module provided by VeriSilicon to facilitate deployment of Neural-Networks on Verisilicon ML accelerators. It serves as the backend binding for runtime frameworks such as Android NN, Tensorflow-Lite, MLIR, TVM and more.