Added grouped conv2d layout inference (#419)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com> Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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d716a1a9f0
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3e8d5e3493
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@ -27,6 +27,7 @@
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#include "tim/transform/layout_inference.h"
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#include "tim/transform/layout_inference.h"
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#include "ops/conv2d_layout_inference.h"
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#include "ops/conv2d_layout_inference.h"
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#include "ops/grouped_conv2d_layout_inference.h"
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#include "ops/reduce_layout_inference.h"
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#include "ops/reduce_layout_inference.h"
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#include "ops/elementwise_layout_inference.h"
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#include "ops/elementwise_layout_inference.h"
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#include "ops/activation_layout_inference.h"
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#include "ops/activation_layout_inference.h"
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@ -205,6 +206,7 @@ std::vector<std::shared_ptr<vx::Tensor>> HandleLayoutInfer(
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std::vector<std::shared_ptr<vx::Tensor>> next_tensors;
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std::vector<std::shared_ptr<vx::Tensor>> next_tensors;
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switch (op_id) {
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switch (op_id) {
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_CONV2D, Conv2d);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_CONV2D, Conv2d);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_GROUPED_CONV2D, GroupedConv2d);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_RELU, Relu);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_RELU, Relu);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_RELU1, Relu1);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_RELU1, Relu1);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_RELU6, Relu6);
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REGIST_LAYOUT_INFERENCE(VSI_NN_OP_RELU6, Relu6);
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@ -0,0 +1,121 @@
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/****************************************************************************
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*
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* Copyright (c) 2020 Vivante Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*****************************************************************************/
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#ifndef TIM_LAYOUT_INFER_GROUPED_CONV2D_LAYOUT_INFERENCE_H_
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#define TIM_LAYOUT_INFER_GROUPED_CONV2D_LAYOUT_INFERENCE_H_
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#include "tim/vx/ops/groupedconv2d.h"
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#include "direct_map_op_impl.h"
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#include "permute_vector.h"
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#include "ops/op_layout_inference.h"
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namespace tim {
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namespace transform {
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class GroupedConv2dLayoutInfer : public OpLayoutInfer {
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public:
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GroupedConv2dLayoutInfer(
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const std::shared_ptr<vx::Operation> op,
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std::shared_ptr<layout_inference_impl::LayoutInferContext>& context)
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: OpLayoutInfer(op, context) {}
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void OnInputs(
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std::vector<std::shared_ptr<vx::Tensor>>& next_tensors) override {
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vx::DataLayout layout = op_->impl()->layout_;
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auto required_pv = MakeShared(4);
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if (layout == vx::DataLayout::CWHN) {
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required_pv = std::make_shared<PermuteVector<4>>(kCWHN2WHCN);
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}
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auto input_tensors = op_->impl()->InputsTensor();
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for (const auto& in : input_tensors) {
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std::shared_ptr<vx::Tensor> infer_tensor;
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std::shared_ptr<IPermuteVector> trans_pv;
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if (in->IsConstTensor() &&
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!(in->GetSpec().attr_ & vx::TensorAttribute::INPUT)) {
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// For bias
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if (in->GetShape().size() == 1) {
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infer_tensor = context_->infer_graph_->CreateTensor(
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in->GetSpec(), in->GetDataRef());
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trans_pv = MakeShared(1);
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} else {
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// For input/weight
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if (!required_pv->IsAligned()) {
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auto src_grouped_conv2d = std::static_pointer_cast<vx::ops::GroupedConv2d>(op_);
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// Support TVM Kernel Layout
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if (src_grouped_conv2d->KernelDataLayout() == vx::DataLayout::OcIcWH) {
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trans_pv = std::make_shared<PermuteVector<4>>(kOcIcWH2WHIcOc);
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infer_tensor = PermuteConstTensor(
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in, trans_pv);
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} else if (src_grouped_conv2d->KernelDataLayout() == vx::DataLayout::IcOcWH) {
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trans_pv = std::make_shared<PermuteVector<4>>(kIcOcWH2WHIcOc);
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infer_tensor = PermuteConstTensor(
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in, trans_pv);
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} else {
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infer_tensor = PermuteConstTensor(in, required_pv);
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trans_pv = required_pv;
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}
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} else {
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infer_tensor = context_->infer_graph_->CreateTensor(
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in->GetSpec(), in->GetDataRef());
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trans_pv = MakeShared(required_pv->Rank());
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}
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}
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} else {
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// For bias
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if (in->GetShape().size() == 1) {
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infer_tensor = context_->GetMapedTensor(in);
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trans_pv = MakeShared(1);
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} else {
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// For input/weight
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auto pv = context_->GetPermuteVector(in);
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auto final_pv = pv->Reverse()->Add(required_pv);
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if (!final_pv->IsAligned()) {
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infer_tensor =
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InsertPermute(context_->GetMapedTensor(in), final_pv);
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trans_pv = required_pv;
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} else {
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infer_tensor = context_->GetMapedTensor(in);
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trans_pv = pv;
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}
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}
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}
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context_->UpdateTensorMap(in, infer_tensor);
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context_->SetPermuteVector(in, trans_pv);
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}
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auto conv2d = op_->Clone(context_->infer_graph_);
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auto otensor_infer = CreateOutputsTensor(required_pv);
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for (const auto& i_src : input_tensors) {
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(*conv2d).BindInput(context_->GetMapedTensor(i_src));
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}
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(*conv2d).BindOutput(otensor_infer[0]);
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context_->SetPermuteVector(op_->impl()->OutputsTensor()[0], required_pv);
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// Add out tensor of src_graph into next_tensor
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next_tensors.push_back(op_->impl()->OutputsTensor()[0]);
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}
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};
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} // namespace transform
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} // namespace tim
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#endif
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