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Fix build issue if 40BIT_VA enabled (#240) 

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
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Sven 2021-12-17 15:00:14 +08:00 committed by GitHub
parent 321a53fd2a
commit e42faad710
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1 changed files with 14 additions and 5 deletions
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17
src/tim/transform/ops/op_layout_inference.cc
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@ -320,17 +320,26 @@ bool OpLayoutInfer::TransposeConstTensorData(
reverse_shape.push_back(input->GetShape()[i]); reverse_shape.push_back(input->GetShape()[i]);
} }
std::vector<uint32_t> perm = KOcHWIc2OcIcHW; std::vector<uint32_t> perm = KOcHWIc2OcIcHW;
std::vector<uint32_t>tmp_vec0 = kOcIcWH2WHIcOc; std::vector<uint32_t> tmp_vec0 = kOcIcWH2WHIcOc;
std::vector<uint32_t>tmp_vec1 = kIcOcWH2WHIcOc; std::vector<uint32_t> tmp_vec1 = kIcOcWH2WHIcOc;
if (pv->AsStdVec() == tmp_vec0) { if (pv->AsStdVec() == tmp_vec0) {
perm = kHWIcOc2OcIcHW; perm = kHWIcOc2OcIcHW;
} else if (pv->AsStdVec() == tmp_vec1) { } else if (pv->AsStdVec() == tmp_vec1) {
perm = kHWOcIc2OcIcHW; perm = kHWOcIc2OcIcHW;
} }
std::vector<vsi_size_t> native_shape_array;
std::vector<vsi_size_t> native_perm;
std::transform(reverse_shape.begin(), reverse_shape.end(),
std::back_inserter(native_shape_array),
[](const uint32_t& i) { return i; });
std::transform(perm.begin(), perm.end(), std::back_inserter(native_perm),
[](const uint32_t& i) { return i; });
vsi_nn_Transpose(out_data.data(), (uint8_t*)(input->GetDataRef()), vsi_nn_Transpose(out_data.data(), (uint8_t*)(input->GetDataRef()),
(uint32_t*)(reverse_shape.data()), native_shape_array.data(),
static_cast<uint32_t>(input->GetShape().size()), static_cast<uint32_t>(input->GetShape().size()),
perm.data(), vx_type); native_perm.data(), vx_type);
return true; return true;
} }