From f52cb852d601207e0f0f86b97a29ff3cb63b1af1 Mon Sep 17 00:00:00 2001
From: chxin66 <57057788+chxin66@users.noreply.github.com>
Date: Mon, 11 Jul 2022 09:55:48 +0800
Subject: [PATCH] Fixed transpose layout inference bug (#430)

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
---
 src/tim/transform/ops/transpose_layout_inference.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/tim/transform/ops/transpose_layout_inference.h b/src/tim/transform/ops/transpose_layout_inference.h
index bda00a4..e926a93 100644
--- a/src/tim/transform/ops/transpose_layout_inference.h
+++ b/src/tim/transform/ops/transpose_layout_inference.h
@@ -69,7 +69,8 @@ class TransposeLayoutInfer : public OpLayoutInfer {
           context_->infer_graph_->CreateOperation<tim::vx::ops::Transpose>(
               final_pv->AsStdVec());
       transpose_op->BindInput(infer_input);
-      auto infer_out = CreateOutputsTensor(final_pv);
+      //  The layout after final_pv permute is the default sequence
+      auto infer_out = CreateOutputsTensor(MakeShared(perm.size()));
       transpose_op->BindOutput(infer_out[0]);
     }
     context_->SetPermuteVector(op_->impl()->OutputsTensor()[0], MakeShared(perm.size()));