Commit Graph

18 Commits

Author SHA1 Message Date
Kee 6810d310d3
update CI workflows to use v4 of the artifact actions (#714) 2025-10-09 18:39:22 +08:00
Chen Feiyue 8494275d76
Update internal ovxlib to release/1.2.22 (#706)
* Update internal ovxlib to release/1.2.22

Signed-off-by: Feiyue.Chen <Feiyue.Chen@verisilicon.com>

* Refine yaml file for blocking tfhub model tests

Signed-off-by: Feiyue.Chen <Feiyue.Chen@verisilicon.com>

---------

Signed-off-by: Feiyue.Chen <Feiyue.Chen@verisilicon.com>
2025-01-08 13:22:46 +08:00
zhongzhuonan e3d891a477
Update self-hosted.yml (#687)
add a TIMEOUT for TIM-VX check. If this step fails, there is a high probability that the local board has problems.There is a TIMEOUT to find problems faster.
2024-03-21 14:22:30 +08:00
Chen Feiyue a24d2be9c3
Rebuild prebuil-sdk to adjust lower ubuntu env (#658)
Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-09 15:44:34 +08:00
zhongzhuonan f0cf45fdaa
Create self-hosted.yml (#625)
* Create self-hosted.yml

* Update self-hosted.yml
2023-07-26 13:31:07 +08:00
Chen Feiyue 33f3a4f176
Enable float16 bias convolution model runs on NN (#612)
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver

Caution: Clang version requires minimum 15.0

Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-30 09:41:28 +08:00
Feiyue Chen 7baf8c307f Fixed tensorflow version in CI
modify fetched tensorflow version to v2.10.0

Type: Bug Fix

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-10-19 18:04:52 +08:00
Kainan Cha a6e04b2116
Update cmake_x86_vsim.yml 2022-09-09 17:24:23 +08:00
ZhangXiang 090f3f21d6 Add ut configuration for cl only device
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
Sven e61d5bd17c
Update cmake_x86_vsim.yml (#403)
Move tensorflow version to v2.9.0
2022-05-30 21:32:19 +08:00
Sven 4f2991c853
Fixed no-output if transpose is last op and can be optimized (#395)
* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-05-13 16:59:25 +08:00
Sven 3f629d3910
Fix ci crash (#380)
* Update and rename cmake_x86_vsim_unit_test.yml to cmake_x86_vsim.yml

* Update README.md

* Update cmake_x86_vsim.yml

* Update README.md

Fix badge
2022-05-03 10:49:49 +08:00
Sven cccd7860d6
CI enhancement - enable benchmark_model and samples (#372)
Added Clang build check with CMAKE
Added vx-delegate build and benchmark_model test for PR.
Added tim-vx/samples in ci
Save output from build for debugging purpose.
Parallel CI execution.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-04-24 12:26:29 +08:00
Kainan Cha f5881c6fa5
Add dispatch_workflow to CI action (#198)
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-22 11:45:04 +08:00
Kainan Cha 2243afcb6e Fix CI badge
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-20 17:20:47 +08:00
Kainan Cha 300850a8fa Add bazel unit test CI
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-20 17:15:33 +08:00
Goose Bomb 914e280209
Refactor CMake build system (#184)
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test
2021-10-12 10:44:49 +08:00
Sven eae539575c
Add CMake UnitTest in CI (#66)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-25 09:48:49 +08:00