Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Fixed bug that when deconv1d ouput is set to be transient, actual output shape will be zero at dim 1.
Reason :internal typing error
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver
Caution: Clang version requires minimum 15.0
Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Add another constructor for stridedslice when new_axis_mask is set
The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Remove unused value to make sure project build successfully with higher
version compiler such as clang15
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Record constructor form of each operation as a json file to support acuity to call
timvx op
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Refine unidirectional_gru and gru_cell code to avoid including ovxlib files
in header of some op
Introduce TranslateToVsibool function to support above code refinement
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
In the past we reverse all inputs to default order pv and caused
unnecessary transpose operation.
In this commit only const slope will be handled and do transpose if necessary.
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added missing ops which have already supported; Changed status of some
ops.
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Support tensor cache while create tensor
Tensor can be shared between different operations, if tensor have
identical data and quantization parameter, they should share same
low-level tensor object to save memory.
In tim-vx, introduce a tensor cache which key is md5sum and value is
low-level tensor object. If up-coming tensor have same md5sum, the
cached tensor object reused for tensor creation.
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
Update internal to 0e9393dbb4f653b9dfceaeaaa920d4deb8b27077
Update prebuilt-sdk to 6.4.14 release
Update cmakefiles to support above updates
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
If graph has free INPUT or OUTPUT, modified error to
warning when check in graph compile
Type: Code refine
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
* Fixed the IOtensor order difference between src_graph and infer_graph
Graph Input/Output tensor sequence may changed after graph
transformation(layout infer), it is difficult to get the IO mapping
between original graph and final graph.
Clients such as the Android Support Library create tensors using the
original input/output order, which may not be the same as the input
order of src_graph, the data can not be setup correctly.
Solution:
Decide the order of inputs/outputs while creating tensor not at binding to
operation. The order of binding could be change in each transform.
Type:Code improvement
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
* Fixed maxpoolgrad maxpoolwithargmax2 cases
Some tensors created with wrong attr
Type: Bug fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
---------
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
Type: New Feature | Bug Fix | Code Improvement | Documentation
Issue: bugzilla id | jira id #No more newline after this
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Modified datatype of copied output so that actual float16 output can be
checked correctly
Type: Bug Fix
Issue: Bug 34696
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Chen Feiyue
chxin66
shijie001
SCUWQ
liyuenan
Zhouheng Zheng
zhouheng.zheng
Chen Xin
ZhangXiang
Feiyue Chen
Tang
meseraph
Huanyu.Cai