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328 Commits

Author SHA1 Message Date
ZhangXiang 090f3f21d6 Add ut configuration for cl only device 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
Tang 128d19b448 update Operators.md 2022-08-02 09:59:15 +08:00
zhouheng.zheng ecfc8735d9 update nbg format version 2022-07-29 12:40:25 +08:00
Chen Xin 27b4298b29 Fixed quantize param in reduce_sum 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-29 11:12:09 +08:00
qin.chen 9ebddb5452 add op: maxpoolwithargmax2 and maxpoolgrad 2022-07-29 11:11:33 +08:00
qin.chen 84d76e5251 fixed: maxpoolwithargmax's output1 have wrong shape, internal id: I7d5aeab58038bacb73373a4ff4f48a12bb6441db 2022-07-29 11:11:33 +08:00
Antkillerfarm 32241dc4ad
Rename RoiAlign & RoiPool (#446) 2022-07-29 11:10:25 +08:00
chxin66 96c9d5df01
Added cases for reduce sum (#441) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:53:56 +08:00
chxin66 cfe8c808bd
Added broadcast layout infernece (#438) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-27 12:52:48 +08:00
liyuenan 7d88a668e3
Update internal for 22Q2 release (#432) 
* Update internal for 22Q2 release

update to internal commit-id: e96103281b08404cabb9b65306587627cfa3cb93

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

* Update prebuilt for 22Q2 release

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-07-25 09:29:22 +08:00
chxin66 9f331ed5ec
Added batch dims in gather (#435) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-19 12:33:09 +08:00
chxin66 f52cb852d6
Fixed transpose layout inference bug (#430) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:55:48 +08:00
chxin66 6344379469
Disabled 3 failed case (#428) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-11 09:54:42 +08:00
liyuenan 24fa582a56
Enable SetRoundingPolicy (#426) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-07-06 17:03:54 +08:00
chxin66 e047fce59f
Disable cases which offloaded to SW path(#422) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-04 15:37:06 +08:00
chxin66 3e8d5e3493
Added grouped conv2d layout inference (#419) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-06-28 14:52:26 +08:00
Antkillerfarm d716a1a9f0
remove redefination of TIM_VX_ENABLE_CUSTOM_OP (#417) 2022-06-27 14:59:46 +08:00
Antkillerfarm 3dd6c507d4
add reshape unit test (#416) 2022-06-23 14:07:38 +08:00
Kainan Cha febc83e084
Fix CI badge 
Fix CI badge issue
 2022-06-15 18:42:17 +08:00
Kainan Cha e21e02bf2c
Update Programming_Guide.md 
Update descriptions about Tensors
 2022-06-11 00:54:29 +08:00
Sven e61d5bd17c
Update cmake_x86_vsim.yml (#403) 
Move tensorflow version to v2.9.0
 2022-05-30 21:32:19 +08:00
MESeraph 11f953b506
Mapped roi_pool & added unit test (#404) 
* Mapped roi_pool & added unit test

* modify roialign/roipool unit test
 2022-05-30 19:57:50 +08:00
chxin66 44cc6f9f09
lstm layout inference & Added unidirectional lstm layout inference (#392) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-29 22:40:43 +08:00
MESeraph 6d0c6b01b5
modify GatherElements (#406) 2022-05-29 22:25:14 +08:00
chxin66 1b4c30e572
Mapped roi_align & added unit test (#402) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-27 16:34:48 +08:00
Dahan Gong f8741b4704
feat(tensor): support external buffer when creating input/output tensors (#389) 
* support external buffer when creating input/output tensors

* feat(tensor): add new map/unmap APIs
 2022-05-18 23:38:26 +08:00
Sven a9764291b0
Fix build issue (#397) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-16 14:24:44 +08:00
Sven 4f2991c853
Fixed no-output if transpose is last op and can be optimized (#395) 
* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-05-13 16:59:25 +08:00
Antkillerfarm b3677305c4
add GetElementNum/GetElementByteSize/GetByteSize for TensorSpec (#393) 2022-05-13 14:29:25 +08:00
chxin66 0d8ac3dc2b
Added gather_elements & unit test (#363) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-10 09:55:50 +08:00
chxin66 60cfea53a0
fix gather_element operation input num issue (#388) 
Change-Id: Id2e685cf6993776e6674f528b71eb842420b16ad

 Author:    Xia Kaihong <kaihong.xia@verisilicon.com>
 Date:      Thu Apr 14 16:23:16 2022 +0800
 2022-05-06 09:31:14 +08:00
Antkillerfarm c6847981e6
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for unit test compatibility (#386) 2022-05-06 09:30:26 +08:00
chxin66 11572140d2
Fixed layout inference bug for stack (#375) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:18:09 +08:00
MESeraph eab0d807a6
Added Ceil & unit test (#381) 
* Added Ceil & unit test

* Added Round & Unit test
 2022-05-05 17:11:31 +08:00
chxin66 7a8ae32f73
Added topk & unit test (#384) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:06:39 +08:00
Zhouheng Zheng c09cdf79ad
fix bug of param num in custom op (#385) 
ref to:https://github.com/VeriSilicon/TIM-VX/issues/378

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-05-05 17:04:38 +08:00
Sven 3f629d3910
Fix ci crash (#380) 
* Update and rename cmake_x86_vsim_unit_test.yml to cmake_x86_vsim.yml

* Update README.md

* Update cmake_x86_vsim.yml

* Update README.md

Fix badge
 2022-05-03 10:49:49 +08:00
lucklee 4bd0ce943b
add test demo for multi_device (#371) 2022-04-29 22:54:03 +08:00
Kainan Cha d108661a03
Update README.md 2022-04-27 13:14:23 +08:00
Antkillerfarm 3f2e67b65f
add macro VSI_EXPAND_BROADCAST_ENABLE_DIMENSIONS for ovxlib compatibility (#374) 2022-04-24 18:38:56 +08:00
Antkillerfarm dbb3631d4e
rename CopyTensorToData to CopyDataFromTensor to align name of tim::vx::Tensor (#373) 2022-04-24 13:36:51 +08:00
Sven cccd7860d6
CI enhancement - enable benchmark_model and samples (#372) 
Added Clang build check with CMAKE
Added vx-delegate build and benchmark_model test for PR.
Added tim-vx/samples in ci
Save output from build for debugging purpose.
Parallel CI execution.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-04-24 12:26:29 +08:00
chxin66 5c4800ab33
Fixed pad layout inference bug & added one stridedslice case (#370) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-20 21:44:43 +08:00
Sven b5c4514b94
Update operator support planw (#367) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-04-19 11:38:07 +08:00
Antkillerfarm b916e1301a
Add Broadcast op (#365) 2022-04-18 15:45:15 +08:00
chxin66 96dedc1453
Added selu & celu & unit test (#366) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-18 14:35:29 +08:00
Antkillerfarm 954d264108
add BroadcastInDim to internal expand_broadcast op (#364) 2022-04-18 13:59:18 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 479fc576ae
Suported specifying CRD_mode & DCR_mode in depthtospace (#362) 
https://github.com/VeriSilicon/TIM-VX/issues/304

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:53:32 +08:00
chxin66 0dc38eac2e
Added unit test for maxpool (#361) 
https://github.com/VeriSilicon/TIM-VX/issues/318

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 22:16:47 +08:00