TIM-VX

Commit Graph

Author	SHA1	Message	Date
Sven	cccd7860d6	CI enhancement - enable benchmark_model and samples (#372 ) Added Clang build check with CMAKE Added vx-delegate build and benchmark_model test for PR. Added tim-vx/samples in ci Save output from build for debugging purpose. Parallel CI execution. Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2022-04-24 12:26:29 +08:00
chxin66	9fdba427f7	Integrate benchmark test of conv2d and depthwise conv2d (#276 ) Signed-off-by: Chen Xin <jack.chen@verisilicon.com> Co-authored-by: Chen Xin <jack.chen@verisilicon.com>	2022-01-21 15:32:23 +08:00
xiang.zhang	853df36bd6	Add simple benchmark test for convolution op Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2021-07-07 14:11:40 +08:00

Author

SHA1

Message

Date

Sven

cccd7860d6

CI enhancement - enable benchmark_model and samples (#372 )

Added Clang build check with CMAKE
Added vx-delegate build and benchmark_model test for PR.
Added tim-vx/samples in ci
Save output from build for debugging purpose.
Parallel CI execution.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

2022-04-24 12:26:29 +08:00

chxin66

9fdba427f7

Integrate benchmark test of conv2d and depthwise conv2d (#276 )

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>

2022-01-21 15:32:23 +08:00

xiang.zhang

853df36bd6

Add simple benchmark test for convolution op

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

2021-07-07 14:11:40 +08:00

3 Commits