96d186c8d2
Set graph attributes when compile graph to binary
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Keep the same graph attributes as compile graph
Signed-off-by: Kee <xuke537@hotmail.com>
2022-08-15 06:34:08 +08:00
f8741b4704
feat(tensor): support external buffer when creating input/output tensors ( #389 )
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* support external buffer when creating input/output tensors
* feat(tensor): add new map/unmap APIs
2022-05-18 23:38:26 +08:00
7c1a00213b
[New API] Add compile_option support - relax_mode ( #285 )
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Added new API for tim::vx::Context::CreateGraph with a CompileOption
Only one option added in CompileOption:
relax_mode : Run float32 mode with bfloat16
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-02-09 10:52:11 +08:00
e2180a6341
Support that op's all inputs are constant ( #264 )
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2022-01-14 12:34:38 +08:00
75d39e2cfd
Support layout inference for transpose ( #250 )
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Added interface GetProdeucerOp(tensor) in Graph
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-29 11:06:28 +08:00
8b1ec74f07
support DMAbuffer ( #214 )
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-11-21 22:46:20 +08:00
77b801a590
Add layout inference feature ( #34 )
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* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-05-08 09:29:47 +08:00
9d44b4477b
Added NBG support
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-02-22 11:38:21 +08:00
7972af0697
Initial Commit for VERSION 1.1.28
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Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-11 18:27:48 +08:00
Kee
Dahan Gong
Sven
liyuenan
chxin66
Zongwu.Yang
Jiang Bo