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54 Commits

Author SHA1 Message Date
Zongwu.Yang 22d423714f
Optimize permute op for constant tensor (#37) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-10 23:06:04 +08:00
Sven 5cfa7a2c40
Cmake build improvement (#36) 
Added "make install" support for cmake
Fixed symbol removed during link because no reference

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-08 23:02:04 +08:00
Kainan Cha 03a53cba7e Minor Cleanup 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-08 12:13:02 +08:00
xiang.zhang b8c892f8c3 Add cmake build for VIM3 android P 
Change cmake/vim3_android.cmake to build other variant(android 10)

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-08 11:46:05 +08:00
xiang.zhang 205f7d53f0 Align declare and definition for TensorSpec 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-08 11:46:05 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
Kainan Cha e5d6da20a7 Minor cleanup 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-06 19:48:36 +08:00
Kainan Cha 31969a7326 Add support for Android make 
This change adds support for building TIM-VX under a
Android AOSP environment.

Instructions below based on Khadas VIMS system

* Add TIM-VX git repository to Android AOSP

  # cd vendor/amlogic/common/npu
  # git clone git@github.com:VeriSilicon/TIM-VX.git tim-vx

* Include tim-vx/Android.mk to AOSP build

  Edit vendor/amlogic/common/npu/Android.mak

    +TMP_PATH := $(LOCAL_PATH)
    +VIVANTE_SDK_DIR := $(LOCAL_PATH)/service/ovx_inc
    +include $(LOCAL_PATH)/tim-vx/Android.mk
    +LOCAL_PATH := $(TMP_PATH)

    ifeq ($(BOARD_NPU_SERVICE_ENABLE), true)

  Note VIVANTE_SDK_DIR needs to point to SDK header
  inclusion path

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-06 18:53:51 +08:00
Kainan Cha 88f83019a8 Use RTNE as default rounding policy 
RTNE, Round To Nearest Even is a better rounding policy
which aligns with implementation of Tensorflow Lite.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-27 15:30:15 +08:00
zhengzhouheng eff71c38bf add argmin and argmax op 2021-04-16 00:34:29 +08:00
yuenan.li c9d3416c6b Add the Squeeze op 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-04-15 11:22:48 +08:00
Jia 11480f18f3 Store operation into graph 
because the operation is a shared pointor, in app, the operation is
created as:
    auto op = graph->CreateOperation();

uses natively think the operation had been register into the graph and
would not manage the op locally.

if running the graph in another fucntion instead of the function that
create the operation, the operation would had been delete.

so the operation should be stored into the graph.

Signed-off-by: Jia <juku.jia@verisilicon.com>
 2021-04-15 11:21:56 +08:00
zhengzhouheng dc67e9ac63 add the Stack op 2021-04-07 19:57:28 +08:00
Kainan Cha 165b3fcf8f Minor clean up 
Fix typos and move functions into appropriate files

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-07 13:03:56 +08:00
zhengzhouheng 07fc3b9914 add the clip, dropout, batchnorm op 2021-04-07 13:00:41 +08:00
Kainan Cha 9dfcb5a230 Add support for S905D3 SoC 
bazel build --config S905D3

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-06 13:30:16 +08:00
Kainan Cha 90a52ea6c9 Add support for Mish, SoftRelu and HardSigmoid 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-31 12:00:02 +08:00
Kainan Cha f92a5de68b Set Graph Version during in Compile() 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:11:06 +08:00
Kainan Cha c569555f1f Use FCL2 instead of FCL which supports axis 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:08:22 +08:00
Kainan Cha c141416238 Update internal to REL/v1.1.30.2 
SHA: 2e64046f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 16:25:12 +08:00
yuenan.li b5f2666e92 Map Select 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-03-25 17:27:04 +08:00
Kainan Cha 0d7afd9d51 Minor cleanup 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-19 11:12:12 +08:00
Kainan Cha cfc70c48df Use auto shape for virtual tensors 
Use auto shape for virtual tensors so that TIM-VX can
perform its internal shape inference and graph
optimizations.

Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-18 14:24:10 +08:00
Kainan Cha b6f0ffaef6 Fix Mutliply API 
Internal ops require a scale parameter to be initialized
to 1.0f.

Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-17 17:56:11 +08:00
yuenan.li f79aac314c Fix bug in tensor attribute setting 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-17 16:50:45 +08:00
yuenan.li 8f1c33ea83 add README.md for op support 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-03-16 11:46:57 +08:00
Kainan Cha 41e4a7d232 Add bazel config to allow injection of external SDK 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-05 11:14:46 +08:00
Kainan Cha f792df34f7 v1.1.30 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-26 17:20:36 +08:00
Jiang Bo def53f4b5c Update internal to REL/v1.1.30 
Commit: 6ccb425e
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-02-26 17:05:14 +08:00
Zongwu.Yang 62898a4419 Update Cmake build dir to PROJECT_BINARY_DIR 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-26 17:04:40 +08:00
BUG1989 6eb067b766 Fix README typo 2021-02-26 15:29:38 +08:00
Kainan Cha c46904c339 Add op support for Deconv2d 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-26 09:54:01 +08:00
Kainan Cha 01fabba95e Rename BUILD.bazel to BUILD 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-26 09:53:32 +08:00
Kainan Cha 4966b2849d Fix README format 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-25 17:54:22 +08:00
Kainan Cha fef9532954 Update README with framework support 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-25 17:50:36 +08:00
Jiang Bo 0dbaae19c5 Link whole archive of tim_internal 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-02-25 15:45:35 +08:00
Zongwu.Yang 8082c43317 Fix cmake build error 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-24 19:06:54 +08:00
zhengzhouheng c8b0180e7a fix the bug of pooling layer output shape mismatch 2021-02-24 10:15:24 +08:00
xiang.zhang 9d44b4477b Added NBG support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-02-22 11:38:21 +08:00
Zongwu.Yang c5e16157a6 Update linking style as static linking for sample 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-08 14:47:37 +08:00
Zongwu.Yang eb01d28a1a Add cross compile for A311D 
* Support auto-downloading toolchain and SDK from http
  * Support one-click cross compilation

Usage:
  mkdir build && cd build
  cmake .. -DHARDWARE=A311D
  make -j4

Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-07 18:52:03 +08:00
Kainan Cha dc9931e126
Merge pull request #9 from zhengzhouheng/main 
support build for tensorflow A311D
 2021-02-07 10:45:44 +08:00
zhengzhouheng 26d3654a6a support build for tensorflow A311D 2021-02-07 10:33:04 +08:00
Zongwu.Yang 5108598fd5 Add Cmake build for tim-vx 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-02 10:04:47 +08:00
Sven 9f70d05765
Merge pull request #7 from liyuenan2333/select 
Support multiply attribute for tensor spec
 2021-02-01 20:18:14 +08:00
yuenan.li bd4d277ac1 Support multiply attribute for tensor spec 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-02-01 14:10:03 +08:00
Jiang Bo 2390ece5ac Support build for A311D 
Add cross compilation support for A311D SoC platform. A prebuilt-sdk
for aarch64 and Linux Kernel version 4.9 is provided.

basel build --config A311D //samples/lenet:lenet_asymu8_cc

Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-01-29 00:11:41 -08:00
Kainan Cha 984ab3b24a Update build instruction in README 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-01-26 06:53:39 -08:00
yuenan.li 44af63b9e9 [NNRT-811]Map Slice 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-01-22 14:32:43 +08:00
hawk081 92e62e78fc
Merge pull request #1 from liyuenan2333/main 
Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd
 2021-01-19 16:53:31 +08:00