colin
/
TIM-VX
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
449 Commits 1 Branch 0 Tags 101 MiB
Commit Graph

17 Commits

Author SHA1 Message Date
MercuryChen 315adcf076
Integrate api trace into tim-vx source as an experimental feature. (#623) 
* Add support for different input dtype of MaxPoolGrad.

Type: Code improvement

* Integrate api trace into tim-vx source code, as part of experimeantal.

Type: New Feature
 2023-07-19 18:40:48 +08:00
Chen Feiyue b81f7979fa
Reload "==" operator for quantizations of two tensor (#583) 
Reload operator "==" to check two quantization same or not

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-05-10 17:58:30 +09:00
SCUWQ 1543efe098
Add some tensor dtype convert APIs (#576) 
For pre/post process.

Type: Code Refine

Co-authored-by: wangqian <wangqian@CNCDD9444.verisilicon.com>
 2023-04-27 09:04:39 +08:00
Zhouheng Zheng e49f67b840
Remove tensor GetDataRef api (#569) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2023-03-23 21:35:30 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Feiyue Chen 113c3722cb supported int16 dfp quantization & added conv2d unit test 2022-09-15 22:15:22 +08:00
Dahan Gong f8741b4704
feat(tensor): support external buffer when creating input/output tensors (#389) 
* support external buffer when creating input/output tensors

* feat(tensor): add new map/unmap APIs
 2022-05-18 23:38:26 +08:00
Antkillerfarm b3677305c4
add GetElementNum/GetElementByteSize/GetByteSize for TensorSpec (#393) 2022-05-13 14:29:25 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-21 22:46:20 +08:00
lilei 8e63e8c8f3 refine tensor to support attribute access 2021-09-27 17:20:41 +08:00
liyuenan fae5cede7a
Support layout inference for ops (#77) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-27 10:33:44 +08:00
Sven 410cd8e516
Refine the cmake build (#63) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-24 13:40:37 +08:00
Kainan Cha d645494dcc Refine support for data copy operation 
* Properly support tensor handle for both input and output
* Fix UT to use size_in_bytes instead of size in elements

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 22:59:36 +08:00
Zongwu.Yang 22d423714f
Optimize permute op for constant tensor (#37) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-10 23:06:04 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
xiang.zhang 9d44b4477b Added NBG support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-02-22 11:38:21 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-11 18:27:48 +08:00