33f3a4f176
Enable float16 bias convolution model runs on NN ( #612 )
...
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver
Caution: Clang version requires minimum 15.0
Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-30 09:41:28 +08:00
d778dfb82d
update copyright information
2023-01-20 12:49:48 +08:00
1802e558ad
modified cumsum header && resolve conflict in README.md
2022-09-26 14:27:48 +08:00
264e491d2a
added cumsum op & added handle api after BindInput
2022-09-26 14:27:48 +08:00
e2180a6341
Support that op's all inputs are constant ( #264 )
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2022-01-14 12:34:38 +08:00
cea11422b8
Added RNNCell & unit test ( #249 )
...
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-12-29 11:08:24 +08:00
e27e15925c
Add unidirectional sequence lstm support
...
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-08-09 13:43:33 +08:00
29f1efc492
add API 'Clone' to tim_vx op and support default layout inference
...
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-07-06 12:29:18 +08:00
37f686c34d
Remove DownScaleSizeRounding type
...
Use RoundType instead of DownScaleSizeRounding.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-05-25 16:48:50 +08:00
77b801a590
Add layout inference feature ( #34 )
...
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-05-08 09:29:47 +08:00
7972af0697
Initial Commit for VERSION 1.1.28
...
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-11 18:27:48 +08:00
Chen Feiyue
Tang
Feiyue Chen
liyuenan
chxin66
xiang.zhang
yuenan.li
zhao.xia
Zongwu.Yang
Jiang Bo