Commit Graph

511 Commits

Author SHA1 Message Date
Peter Kjellerstedt 3c83eca946
Add include of cstdint to permute_vector.h (#711)
This avoids the following error with GCC 15:

  src/tim/transform/ops/../permute_vector.h:41:11: error: 'uint32_t'
  does not name a type
     41 |   virtual uint32_t Rank() const = 0;
        |           ^~~~~~~~
  src/tim/transform/ops/../permute_vector.h:32:1: note: 'uint32_t' is
  defined in header '<cstdint>'; this is probably fixable by adding
  '#include <cstdint>'
     31 | #include <string>
    +++ |+#include <cstdint>
     32 |

Co-authored-by: Peter Kjellerstedt <pkj@axis.com>
2025-10-13 13:15:57 +08:00
Kee c4e75674fa
Refine platform code and samples (#713)
* Refine platform code and samples

1. Support viplite v2 API
2. Unify the Lite and Native platform APIs so that the same code
   can run on different platforms through different compilation options.

Type: Code Improvement

Signed-off-by: Kee <xuke537@hotmail.com>

* Fix build error if VSI device API is not supported

Signed-off-by: Kee <xuke537@hotmail.com>

---------

Signed-off-by: Kee <xuke537@hotmail.com>
2025-10-13 13:15:31 +08:00
Kee 6810d310d3
update CI workflows to use v4 of the artifact actions (#714) 2025-10-09 18:39:22 +08:00
Chen Feiyue 8494275d76
Update internal ovxlib to release/1.2.22 (#706)
* Update internal ovxlib to release/1.2.22

Signed-off-by: Feiyue.Chen <Feiyue.Chen@verisilicon.com>

* Refine yaml file for blocking tfhub model tests

Signed-off-by: Feiyue.Chen <Feiyue.Chen@verisilicon.com>

---------

Signed-off-by: Feiyue.Chen <Feiyue.Chen@verisilicon.com>
2025-01-08 13:22:46 +08:00
Kainan Cha 149834832c
Update README.md
Add ONNX Runtime Link
2024-12-12 09:24:49 +08:00
Chen Feiyue fcdf223d06
Fixed layernorm and logsoftmax ut error (#702)
Type:  Bug Fix

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-07-29 10:44:28 +08:00
Chen Feiyue 81b6c07c5d
Update timvx_overview.svg (#701)
Type: Documentation

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-07-29 10:44:04 +08:00
Chen Feiyue 720fe0306f
Update timvx-overview (#700)
Type: Documentation

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-07-08 09:31:08 +08:00
Chen Feiyue c8b7c410bf
Update internal ovxlib to rel/1.2.14 (#699)
Type:  New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-07-08 09:29:24 +08:00
Chen Feiyue 8894360c74
Adding api-compatible guarding for updated ops (#695)
* Fixed typing error in gather test

Deleted the external output tensor creation in scalar_1d test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>

* Added ifdef marco for some later added ops

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>

---------

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-05-22 09:51:58 +08:00
Chen Feiyue e1c2f0a18d
Revert ovxlib topk kernel modification (#694)
Internal ovxlib commit:b12b1f138e66c78e0fb4032e5399a68a7280a801 is
revert for sw compatibility

Type:  Bug Fix

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-04-27 07:54:30 +08:00
Chen Feiyue 3b80968fb1
Updata internal ovxlib to rel1.2.6 (#690)
Internal ovxlib commit hash: c5d3e69356579fc7b595a7c0939fc7e4e0aaab5a

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-04-02 19:56:46 +08:00
Antkillerfarm 3ea908ca6d
Add some trigonometric ops (#689)
Add cos/tan/arctan/arctanh/arccosh

Type: New Feature

Signed-off-by: Tang Jing <jing.tang@verisilicon.com>
2024-04-01 15:56:50 +08:00
Antkillerfarm 9294608e52
add unit case for maxpool (#683)
maxpool unit test: kernel 3x3, stride 2x2, dtype=fp16, pad type: valid, round type: floor

Type: Unit Test

Signed-off-by: Tang Jing <jing.tang@verisilicon.com>
2024-03-31 10:05:16 +08:00
zhongzhuonan e3d891a477
Update self-hosted.yml (#687)
add a TIMEOUT for TIM-VX check. If this step fails, there is a high probability that the local board has problems.There is a TIMEOUT to find problems faster.
2024-03-21 14:22:30 +08:00
Chen Feiyue 8ca1382474
Added Asymmetric perchannel quantization support (#682)
Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-02-27 09:37:33 +08:00
Antkillerfarm 3b74cf01fb
add unit test for conv2d (#681)
conv2d unit test: kernel 1x1, stride 2x2, dtype=fp16

Type: Unit Test

Signed-off-by: Tang Jing <jing.tang@verisilicon.com>
2024-02-20 16:50:19 +08:00
Chen Feiyue b4b4f00f47
Added opjson and bug fix for scatternd_onnx_v16 (#678)
Fixed typing error of missed param in this op's clone function

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-01-12 11:49:46 +08:00
Chen Feiyue 0d8ca44377
Fixed layout infer bug when some op is not in op_vector_ (#676)
Backgroud: instance_norm models run crash after latest lay out code
refine

Reason: erase() function will delete the last element if the param is vector.end()

Solution: Check iterator validtion before erase.

Type:  Bug Fix
Issue: 37449

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-01-11 15:58:29 +08:00
Yunshan 394cedcfe6
Add NBG runner python binding (#677)
Co-authored-by: Xiaoran Weng <xiaoran.weng@verisilicon.com>
2024-01-10 16:31:28 +08:00
Chen Feiyue 54b9c6750e
Fixed unreasonable type of parameter in broadcast (#505)
Change type of shape from int to uint & add ut for broadcast
From github issue https://github.com/VeriSilicon/TIM-VX/issues/376
Define opversion to avoid incompatibility with upper level software

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-01-04 21:38:05 +08:00
Chen Feiyue e8dab60cf2
Update ops which has addings in internal (#675)
Added Tan Cos operaion
Added reduction param in scatternd_onnx_v16
Added R2X bias in bidirectional_lstm

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-01-03 16:37:35 +08:00
Chen Feiyue 2d9e614a06
Update internal ovxlib to rel/1.2.2 (#674)
Update to SHA:806fcd6a69d333e62508acf0a6aa2c38c8385eae

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-01-03 13:13:15 +08:00
Zhouheng Zheng cf099e3849
Add license declaration of third party (#672)
Type: Bug Fix
2024-01-03 13:09:52 +08:00
Chen Feiyue 9b945633d7
Fixed typing error and added missed opheader (#673)
Correct file name of moments operation
Added groupedconv1d header in ops.h

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2024-01-03 09:47:47 +08:00
Zhouheng Zheng 4f4f6cd6dc
Add json third party when support node trace db (#670)
Type: Code Improvement
2023-12-20 21:26:42 +08:00
Yunshan feaf06365b
Refine layout inference (#671)
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance

* Keep graph output order in layout inference

Type: Code Improvement

* Fix typos in layout inference

Type: Code Improvement

---------

authored-by: Xiaoran Weng <Xiaoran.Weng@verisilicon.com>
2023-12-20 21:26:16 +08:00
Zhouheng Zheng 622c472edf
Add uid() api for class operation (#668)
Type: Code Improvement
2023-12-18 22:32:21 +08:00
chxin66 11d12f03a8
fix layoutinfer crash when logical op inputs are different rank (#667)
Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-12-13 09:57:17 +08:00
chxin66 0dc7a3465e
fix const tensor align bug in AlignPermuteVectorForElementWise (#666)
* fix const tensor align bug in AlignPermuteVectorForElementWise

Signed-off-by: Chen <jack.chen@verisilicon.com>

* fix build issue use android ndk

Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>

* Fix inappropriate comments for reduce layoutinfer

Type: Code refine

Signed-off-by: Chen <jack.chen@verisilicon.com>

---------

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-12-11 16:59:37 +08:00
chxin66 720f0a485a
fix crash when eletwise inputs are different rank (#665)
Fix crash in AlignPermuteVectorForElmentWise() if inputs tensor have different rank

Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
2023-12-06 17:15:15 +08:00
chxin66 e013cf0a65
fix slope shpae 1 crash issue (#663)
graph compile will crash when shape is broadcast from 1 to 1,1,1,1

Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-12-05 09:35:10 +08:00
Chen Feiyue 4578f40953
Added 2 cases for stack (#664)
Added int32 and uint8 ut for stack op

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-30 15:01:33 +08:00
Chen Feiyue 517397949d
Fix the instance norm test input size bug in layout infer test (#661)
Correct gamma and beta size in InstanceNorm.nhwc case

Type: Bug Fix
Issue: 37103

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-22 09:20:27 +08:00
chxin66 74e2740daa
add a case for resize bilinear (#662)
Type: Code improvement

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-11-21 21:39:42 +08:00
Chen Feiyue 8267effdfb
Refine RNNCell/HardSwish/Reduce_sum ut (#660)
Modify tolerance in some of these op unit tests for StreamProcessor

Type: Bug Fix
Issue: 37103

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-21 16:18:22 +08:00
Chen Feiyue 4fde0badb2
Refine UnitTest which have acc issue or unspport issue in sp (#659)
1.Skip elementwise/relational op unittest if input/output have INF which sp cannot
handle
2.Set different tolerance in Layernom/SoftMax/GRU unittest if SP supported

Type: Bug Fix
Issue: 37103

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-20 14:42:41 +08:00
Chen Feiyue a24d2be9c3
Rebuild prebuil-sdk to adjust lower ubuntu env (#658)
Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-09 15:44:34 +08:00
Chen Feiyue bb10884f98
Added scalar type support (#655)
Added SetScalar api to support scalar input
Added 2 cases for scalar index Gather

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-06 09:58:03 +08:00
Chen Feiyue 1bb1e070f2
Update internal to 1.1.88 release (#657)
Internal ovxlib SHA 32fe479af5549e894bcd40de5740ae0dfd42bdb9

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-11-03 13:16:33 +08:00
xie-oritek 10081790ee
Add ScatterND_Update operator (#652)
* Add ScatterND_Update operator

* Remove ScatterNDUpdate shape param

* Rename ScatterND_Update to ScatterND_ONNX_V16

* Fix ScatterND_ONNX_V16 rename problem

---------

Co-authored-by: unknown <z0026@china.oritek.com.cn>
2023-10-11 09:12:40 +08:00
chxin66 363c369bf6
Fixed quant param lost in Bidirectional lstm (#649)
https://github.com/VeriSilicon/TIM-VX/issues/647

Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
2023-09-19 22:08:34 +08:00
Chen Feiyue 61ea0091ca
Fixed unsupported float16 bias in fc (#646)
Resolve the issue of underlying hardware not supporting float16 bias in fc
by converting bias type to float32

Type: Code Improvement

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-09-13 09:44:21 +08:00
Antkillerfarm 98966dac9c
build fix for export Swap Handle API (#643)
PR #635 build error fix

Type: bug fix

Signed-off-by: Tang Jing <jing.tang@verisilicon.com>
2023-08-30 14:25:45 +08:00
chxin66 01235266c5
fixed tensor cache mismatch issue (#644)
Type: Bug fix

Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-08-30 14:23:20 +08:00
Zhouheng Zheng 5668856fc9
Fix the instance norm test input size bug (#645)
Only NNAPI instance norm spec have scalar gamma and beta, which can not
support by sp, rewrite it into tensor.

Type: Bug Fix

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
2023-08-30 14:10:23 +08:00
Antkillerfarm 3bbe2ef9ec
export Swap Handle API (#635)
export vsi_nn_SwapHandle & vsi_nn_SwapTensorHandle &
vsi_nn_SwapTensorHandleWithCache for TIM-VX usage.

Type: New Feature

Signed-off-by: Tang Jing <jing.tang@verisilicon.com>
2023-08-28 09:15:43 +08:00
xie-oritek 7fc264a9e6
Refine Tensor::SetShape api to avoid compile warning using const ref (#640)
* Move int4/uint4 to the end of DataType

* Refine api Tensor::SetShape, using const ref avoid compile warning
2023-08-25 00:47:24 +08:00
MercuryChen 6f34b66ae4
Split replayer code from tracer.h (#642)
* Add support for different input dtype of MaxPoolGrad.

Type: Code improvement

* Integrate api trace into tim-vx source code, as part of experimeantal.

Type: New Feature

* Refine api trace code and document
Add missing traced apis of tim::vx::Quantization

Type: Code improvement

* Split Api relayer code out of tracer.
To enable compile replayer code in machine which can't access high version boost libs.

Type: Code improvement
2023-08-25 00:41:45 +08:00
xie-oritek 265e74ff16
Add int4/uint4 definition (#638) 2023-08-22 17:37:38 +08:00