Commit Graph

176 Commits

Author SHA1 Message Date
Kainan Cha 47191227e0 Release 1.1.34
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-08 12:36:02 +08:00
Kainan Cha ec77be3a31
Update prebuilt SDK x86_64 to 6.4.8
Update prebuilt-SDK to 6.4.8

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-08 11:57:41 +08:00
Kainan Cha d7900b9de4 Add sample to run NBG
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-09-27 17:21:04 +08:00
lilei 8e63e8c8f3 refine tensor to support attribute access 2021-09-27 17:20:41 +08:00
Kainan Cha 404817db1f Remove unused directories from CMake
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-09-24 22:02:11 +08:00
Kainan Cha 81cc868b6c Update internal to 1.1.34
SHA: 67f1e

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-09-24 21:36:18 +08:00
Sven d841b85859
Update README.md
Add support information.
2021-09-22 09:43:10 +08:00
lilei 073a79f463 add ops.h to contain all operation header file 2021-09-17 22:41:44 +08:00
xiang.zhang 994f8a9c2a Fixed layout inference crash(assert) if node have multiply output
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-09-16 10:55:29 +08:00
xiang.zhang 374841cbd9 Fix build error with Android NDK
Verified with android ndk r22b

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-09-09 12:56:01 +08:00
Chen Xin 633075f689 delete Non-approximate option, recommend to use
the approximate option

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-09-07 22:44:57 +08:00
Chen Xin 6f2e92ffa6 Add shuffle_channel support & test for tim::vx
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-09-07 22:44:57 +08:00
xiang.zhang b226777ad3 Fix average_pool unit test failure: precesion issue
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-08-30 19:53:01 +08:00
Kainan Cha ff22b3e34c Update README
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-08-26 16:33:54 +08:00
Chen Xin eb28f8b3ed move ArraysMatch function into src/tim/vx/test_utils.h
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-08-26 16:28:08 +08:00
Chen Xin 3d64cfc4ef add avgpool test
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-08-26 16:28:08 +08:00
Johan Gunnarsson 0a26a12f94
Don't overwrite CMAKE_CXX_FLAGS (#159) 2021-08-24 22:40:36 +08:00
Antkillerfarm fa930678ea
add Programming_Guide.md & Operators.md (#157) 2021-08-24 12:42:46 +08:00
chxin66 5e09e98c1a
Add Gelu support for tim::vx (#153)
* Add map for Gelu

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-08-17 20:37:12 +08:00
jing.tang a364c3eafb add Swish op 2021-08-16 19:30:14 +08:00
Jing.Deng 4d53e042c8 add the customer case.(only include wrong case)
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
2021-08-13 11:57:57 +08:00
xiang.zhang e27e15925c Add unidirectional sequence lstm support
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-08-09 13:43:33 +08:00
xiang.zhang d4a13e18a9 Minor refinement: use tensor pointer after check
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-08-04 11:31:26 +08:00
jing.tang f0d4118f87 Update ops doc for internal 1.1.32.1 2021-08-04 11:30:45 +08:00
Kainan Cha c294c78779 Update README
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-08-03 12:49:46 +08:00
Kainan Cha 6a949bb315 Add align_corners support for SpatialTransformer
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-08-03 10:52:51 +08:00
Kainan Cha 4d4bc08d6a Update internal to 1.1.32.1
SHA: 215204

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-08-02 16:19:21 +08:00
zhao.xia 8fb3a7e6fb Remove customer test
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-07-30 11:19:32 +08:00
Your Name 70c427256d Fix groupconv2d pad parameter 2021-07-29 17:23:45 +08:00
Chen Xin a09ffe8b98 addn unit test
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-07-22 10:41:25 +08:00
Jing.Deng 3a0bc515a1 add unit test for customer use case
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
2021-07-22 09:55:48 +08:00
Kainan Cha 47119a569d Update version 1.1.32
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-07-13 19:19:46 +08:00
Zongwu Yang d2ea2ff7d3 Add multi thread test
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-07-13 09:17:35 +08:00
Jing.Deng f9cb2dbe45 fix the axis issue about perchannel quantized conv2d
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
2021-07-09 14:56:39 +08:00
xiang.zhang 68228c04d4 Add Bazel build support for benchmark_test
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-07-07 14:11:40 +08:00
xiang.zhang 853df36bd6 Add simple benchmark test for convolution op
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-07-07 14:11:40 +08:00
yuenan.li 2f8f87d1cb Add Clone API for SpatialTrasformer
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-07-06 17:34:57 +08:00
zhao.xia 8aa11f5f29 Support SpatialTransformer
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-07-06 12:56:28 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-07-06 12:29:18 +08:00
zhao.xia 21ecf5262e Add map for Matmul
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-06-29 16:06:35 +08:00
zhao.xia 3fa2bf519a Add map for moments
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
2021-06-29 15:58:51 +08:00
Kainan Cha 3c59694025 Update internal to 1.1.32
SHA: 9aa0b0f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-06-29 11:25:36 +08:00
yuenan.li 98b9759663 Refine arg in layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-29 11:24:28 +08:00
Jing.Deng be066fb9bd add float32, uint8 and int8 unit_tests for transposeConv2d
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
2021-06-24 21:27:16 +08:00
yuenan.li 1e42cfd668 Support layout inference for nbg
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-24 17:28:02 +08:00
xiang.zhang d4de6c78e0 Disable UT for A311D/S905D3/vim3_android/Yocto
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-06-23 19:19:26 +08:00
yuenan.li f8f2c6d519 Fix layout inference for traspose convolution
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-06-21 17:14:16 +08:00
Jing.Deng 1672ef99ed add uint8 and int8 unit_test for depthwise convolution. modify the api of 'conv2d' constructor
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
2021-06-18 14:10:11 +08:00
xiang.zhang 574c036a69 Fix FullyConnect layer crash
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-06-16 16:05:16 +08:00
Robert Kalmar 64989c6b4a Added option to use extenal OVXLIB library
Signed-off-by: Robert Kalmar <robert.kalmar@nxp.com>
2021-06-16 15:00:35 +08:00