TIM-VX

Commit Graph

Author	SHA1	Message	Date
Sven	4f2991c853	Fixed no-output if transpose is last op and can be optimized (#395 ) * Fixed no-output if transpose is last op and can be optimized If transpose can be erased by layout inference, replace it as a reshape - input and output have same shape - expect low-level optimization erase the reshape Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2022-05-13 16:59:25 +08:00
liyuenan	6275f84575	Fix the conflict for previous two commits (#253 ) Signed-off-by: yuenan.li <yuenan.li@verisilicon.com> Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>	2021-12-29 15:38:42 +08:00
liyuenan	75d39e2cfd	Support layout inference for transpose (#250 ) Added interface GetProdeucerOp(tensor) in Graph Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>	2021-12-29 11:06:28 +08:00

Author

SHA1

Message

Date

Sven

4f2991c853

Fixed no-output if transpose is last op and can be optimized (#395 )

* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

2022-05-13 16:59:25 +08:00

liyuenan

6275f84575

Fix the conflict for previous two commits (#253 )

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>

2021-12-29 15:38:42 +08:00

liyuenan

75d39e2cfd

Support layout inference for transpose (#250 )

Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

2021-12-29 11:06:28 +08:00

3 Commits