Commit Graph

11 Commits

Author SHA1 Message Date
chxin66 6424ef104e
Fixed the IOtensor order difference between src_graph and infer_graph
* Fixed the IOtensor order difference between src_graph and infer_graph

Graph Input/Output tensor sequence may changed after graph
transformation(layout infer), it is difficult to get the IO mapping
between original graph and final graph.

Clients such as the Android Support Library create tensors using the
original input/output order, which may not be the same as the input
order of src_graph, the data can not be setup correctly.

Solution:
Decide the order of inputs/outputs while creating tensor not at binding to
operation. The order of binding could be change in each transform.

Type:Code improvement

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

* Fixed maxpoolgrad maxpoolwithargmax2 cases

Some tensors created with wrong attr

Type: Bug fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

---------

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-21 09:21:15 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Kee 96d186c8d2 Set graph attributes when compile graph to binary
Keep the same graph attributes as compile graph

Signed-off-by: Kee <xuke537@hotmail.com>
2022-08-15 06:34:08 +08:00
Dahan Gong f8741b4704
feat(tensor): support external buffer when creating input/output tensors (#389)
* support external buffer when creating input/output tensors

* feat(tensor): add new map/unmap APIs
2022-05-18 23:38:26 +08:00
Sven 7c1a00213b
[New API] Add compile_option support - relax_mode (#285)
Added new API for tim::vx::Context::CreateGraph with a CompileOption

Only one option added in CompileOption:
    relax_mode : Run float32 mode with bfloat16

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-02-09 10:52:11 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2022-01-14 12:34:38 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250)
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-29 11:06:28 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-11-21 22:46:20 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34)
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-05-08 09:29:47 +08:00
xiang.zhang 9d44b4477b Added NBG support
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-02-22 11:38:21 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-11 18:27:48 +08:00