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6 Commits

Author SHA1 Message Date
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
jing.tang 3339135c82 add docs for ops 2021-05-21 18:39:59 +08:00
jing.tang a85fe89cf6 add docs for ops 2021-05-21 18:39:59 +08:00
liyuenan 55ef50385e
Change back the inferface name (#44) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-14 20:08:53 +08:00
liyuenan 748274143b
support layout inference for operations (#39) 
Add layout inference support for space2depth, depth2space, space2batch, batch2space, pad and
reduce.

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-13 22:27:23 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-11 18:27:48 +08:00