680e8d59cb
Fixed conv2d grouped_conv2d deconv2d layoutinfer bug ( #622 )
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-07-24 17:10:24 +08:00
ea8046ec9c
Added roi_align layoutinfer & cases ( #615 )
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* Added roi_align layoutinfer & cases
Type: New feature
Signed-off-by: Chen <jack.chen@verisilicon.com>
* Update instancenorm op spec .json
Type: bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
* Added roi_pool layoutinfer & fixed case bug
Type: new feature
Signed-off-by: Chen <jack.chen@verisilicon.com>
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-07-08 23:39:56 +08:00
a64a0f7379
Added a case for resize_bilinear layoutinfer ( #595 )
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-06-02 07:52:06 +08:00
ea8adc456a
fixed instance norm bug & add its layoutinfer ( #593 )
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Type: Bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-31 12:55:42 +08:00
f1fd2246ae
Support tensor cache while create tensor ( #574 )
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Support tensor cache while create tensor
Tensor can be shared between different operations, if tensor have
identical data and quantization parameter, they should share same
low-level tensor object to save memory.
In tim-vx, introduce a tensor cache which key is md5sum and value is
low-level tensor object. If up-coming tensor have same md5sum, the
cached tensor object reused for tensor creation.
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-04-19 21:31:25 +08:00
5e7f5cecea
Fixed grouped_conv2d layout infer & Added cases
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added cases for conv2d/grouped_conv2d
Type: Bug fixed
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-01-20 15:28:21 +08:00
0e211c8efd
Fixed (groupd)conv2d layout infer bug
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And added a weight_as_input case to test
Type: Bug Fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-16 15:20:56 +08:00
a42517fdce
Align directory name to namespace for layout inference ( #38 )
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-05-11 09:46:46 +08:00
chxin66
Chen Xin
Sven