7baf8c307f
Fixed tensorflow version in CI
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modify fetched tensorflow version to v2.10.0
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-10-19 18:04:52 +08:00
3fed6d6757
fixed bug when broadcast dimensions is negative
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-10-08 21:42:02 +08:00
a038df2a84
added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429
2022-10-08 14:47:07 +08:00
20db77ee61
Added two cases in strided_slice
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-29 20:24:09 +08:00
535c9da867
Fixed bug when input's index is not 0
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-28 16:48:16 +08:00
4c6299e7fd
Added two reduce layout infer unittest
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-28 09:37:38 +08:00
72f2c5b69e
Supported composed layout infer & added unit test
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Fixed fc layout infer in rnncell layout infer
2022-09-26 14:29:46 +08:00
1802e558ad
modified cumsum header && resolve conflict in README.md
2022-09-26 14:27:48 +08:00
264e491d2a
added cumsum op & added handle api after BindInput
2022-09-26 14:27:48 +08:00
9cb37b920f
added MaxPool3d op
2022-09-26 13:32:56 +08:00
8b8d09aea3
added Rcp op & modified test_utils
2022-09-22 12:15:02 +08:00
1b07b022e2
added sign & softsign
2022-09-20 22:49:45 +08:00
f4d5e170de
added & modified copyright of some files
2022-09-20 22:47:33 +08:00
84b464ee8b
Update README.md
2022-09-20 22:47:33 +08:00
6099022f00
added Mod op & Mod unit test
2022-09-20 22:47:33 +08:00
9b13b6f677
Replace name direct_map_op with builtin_op
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-19 10:21:19 +08:00
113c3722cb
supported int16 dfp quantization & added conv2d unit test
2022-09-15 22:15:22 +08:00
95401036ab
fixed some errs on gcc12
2022-09-15 21:26:43 +08:00
6d9ed7b25b
Disabled a conv3d case
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because of some branches are not fully supported
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-15 10:46:05 +08:00
a6e04b2116
Update cmake_x86_vsim.yml
2022-09-09 17:24:23 +08:00
a7a7e15793
Update OpenCV usage link ( #477 )
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https://github.com/opencv/opencv/wiki/TIM-VX-Backend-For-Running-OpenCV-On-NPU
2022-09-07 13:14:45 +08:00
0bb547b8e4
disabled two Div cases
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int32 type not supported in branch 234062
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-06 23:58:03 +08:00
e62b62015d
Added conv3d unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-06 11:45:24 +08:00
e9771746ba
Fix error in feature compatiable guard
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-09-05 15:05:50 +08:00
f348c8e36c
disabled two not supported cases
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-05 14:52:59 +08:00
9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable ( #471 )
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Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-09-01 18:56:49 +08:00
f6121140b0
Mapped unidirectional gru & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-31 09:27:05 +08:00
58395cf7a7
Modified bidirectional_sequence_lstm golden accuracy
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-31 09:26:07 +08:00
80fed36ea3
Modified Div_int unit test golden
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Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
2022-08-30 10:28:09 +08:00
562d0d43b0
Update Version to 1.1.50 ( #462 )
2022-08-22 17:41:43 +08:00
1c640c6f10
Mapped bidirectional lstm & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-22 10:42:05 +08:00
d4f9d7475f
Update version number to 1.1.42
2022-08-16 11:29:47 +08:00
96d186c8d2
Set graph attributes when compile graph to binary
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Keep the same graph attributes as compile graph
Signed-off-by: Kee <xuke537@hotmail.com>
2022-08-15 06:34:08 +08:00
5482760ba2
include Topk op's header file
2022-08-15 06:29:55 +08:00
944fdfad8f
Mapped GRUCell & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-11 20:34:19 +08:00
03b5ec2d17
Added div int32 unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-11 14:37:34 +08:00
a5ba633fe4
add readme for ovxlib_bin_build.sh
2022-08-08 16:52:45 +08:00
9a28ff5758
Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2022-08-08 16:50:25 +08:00
3663a99e0f
Fixed param compute bug for lrn
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-04 21:35:59 +08:00
f728e1b42d
Update overview diagram
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Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
6d47ee3ac1
Expose hw feature : isClOnly()
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Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
090f3f21d6
Add ut configuration for cl only device
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Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
128d19b448
update Operators.md
2022-08-02 09:59:15 +08:00
ecfc8735d9
update nbg format version
2022-07-29 12:40:25 +08:00
27b4298b29
Fixed quantize param in reduce_sum
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-07-29 11:12:09 +08:00
9ebddb5452
add op: maxpoolwithargmax2 and maxpoolgrad
2022-07-29 11:11:33 +08:00
84d76e5251
fixed: maxpoolwithargmax's output1 have wrong shape, internal id: I7d5aeab58038bacb73373a4ff4f48a12bb6441db
2022-07-29 11:11:33 +08:00
32241dc4ad
Rename RoiAlign & RoiPool ( #446 )
2022-07-29 11:10:25 +08:00
96c9d5df01
Added cases for reduce sum ( #441 )
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2022-07-27 12:53:56 +08:00
cfe8c808bd
Added broadcast layout infernece ( #438 )
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2022-07-27 12:52:48 +08:00
Feiyue Chen
Chen Xin
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