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11 Commits

Author SHA1 Message Date
Sven 7c1a00213b
[New API] Add compile_option support - relax_mode (#285) 
Added new API for tim::vx::Context::CreateGraph with a CompileOption

Only one option added in CompileOption:
    relax_mode : Run float32 mode with bfloat16

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-09 10:52:11 +08:00
onepick 7fa5223943
Disable float32 to float16 conversion by default(#267) 
Disable conversion since this will impact the precision. User should enable this conversion explicitly.

Signed-off-by: Jia <juku.jia@verisilicon.com>

Co-authored-by: Jia <juku.jia@verisilicon.com>
 2022-01-14 17:18:16 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-14 12:34:38 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250) 
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 11:06:28 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-21 22:46:20 +08:00
Chen Xin 6f2e92ffa6 Add shuffle_channel support & test for tim::vx 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
Kainan Cha f92a5de68b Set Graph Version during in Compile() 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:11:06 +08:00
xiang.zhang 9d44b4477b Added NBG support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-02-22 11:38:21 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-11 18:27:48 +08:00