* Fixed typing error in gather test
Deleted the external output tensor creation in scalar_1d test
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Added ifdef marco for some later added ops
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
---------
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
add a TIMEOUT for TIM-VX check. If this step fails, there is a high probability that the local board has problems.There is a TIMEOUT to find problems faster.
Backgroud: instance_norm models run crash after latest lay out code
refine
Reason: erase() function will delete the last element if the param is vector.end()
Solution: Check iterator validtion before erase.
Type: Bug Fix
Issue: 37449
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Change type of shape from int to uint & add ut for broadcast
From github issue https://github.com/VeriSilicon/TIM-VX/issues/376
Define opversion to avoid incompatibility with upper level software
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added Tan Cos operaion
Added reduction param in scatternd_onnx_v16
Added R2X bias in bidirectional_lstm
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Remove unnecessary compiler flags
* Refactor CMakeLists.txt
* Tweak CMakeLists.txt for libtim_internal
* Tweak CMakeLists.txt for libtim-vx
* Make TIM_VX_ENABLE_TEST defaults to OFF
* Eliminate usage of include_directories
* Fix CI unit test
* Fix warnings relating to inheritance
* Keep graph output order in layout inference
Type: Code Improvement
* Fix typos in layout inference
Type: Code Improvement
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authored-by: Xiaoran Weng <Xiaoran.Weng@verisilicon.com>
graph compile will crash when shape is broadcast from 1 to 1,1,1,1
Type: Bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
Modify tolerance in some of these op unit tests for StreamProcessor
Type: Bug Fix
Issue: 37103
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
1.Skip elementwise/relational op unittest if input/output have INF which sp cannot
handle
2.Set different tolerance in Layernom/SoftMax/GRU unittest if SP supported
Type: Bug Fix
Issue: 37103
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added SetScalar api to support scalar input
Added 2 cases for scalar index Gather
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Resolve the issue of underlying hardware not supporting float16 bias in fc
by converting bias type to float32
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Only NNAPI instance norm spec have scalar gamma and beta, which can not
support by sp, rewrite it into tensor.
Type: Bug Fix
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
* Refine api trace code and document
Add missing traced apis of tim::vx::Quantization
Type: Code improvement
* Split Api relayer code out of tracer.
To enable compile replayer code in machine which can't access high version boost libs.
Type: Code improvement
Correct erros of deconv1d unittest
Added hint in the header indicating that padtype is not supported yet
Added 2 cases for deconv1d
Type: Code Improvement
Issue: github issue #585
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
* Refine api trace code and document
Add missing traced apis of tim::vx::Quantization
Type: Code improvement
1.Added copyright && Added reference or const reference for functions
2.Rewrite function of determing whether there is a common input
3.Use std::remove_if instead of std::find before doing erase
4.Added security check to prevent access to deleted ops
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added Float16 type definition from third-party
Refine float16 bias handlling in conv2d
Refine float16 case in conv2d
Caution: Headers of float16 only be included when build unit_test
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Chen Feiyue
Antkillerfarm
zhongzhuonan
Yunshan
Zhouheng Zheng
chxin66
xie-oritek
MercuryChen