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505 Commits

Author SHA1 Message Date
Chen Xin 5e7f5cecea Fixed grouped_conv2d layout infer & Added cases 
added cases for conv2d/grouped_conv2d

Type: Bug fixed

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-01-20 15:28:21 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
meseraph 20f759e58a fix depth2space mode enum 2023-01-17 22:44:44 +08:00
Huanyu.Cai 9ab00a57a6 Fixed Invalid read of size 8 reported by Valgrind 2023-01-11 21:31:31 +08:00
Chen Xin 58d36ab943 Added reduce_all layoutinfer & reduce cases 
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2023-01-09 09:30:44 +08:00
Feiyue Chen 789d4458ff Added 4d quantized LUT unittest for embedding_lookup 
Type: New Feature | Bug Fix | Code Improvement | Documentation
Issue: bugzilla id | jira id #No more newline after this
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-01-09 09:28:45 +08:00
Feiyue Chen 06d4747b31 Fixed wrong type of hashtable_lookup unit test 
Modified datatype of copied output so that actual float16 output can be
checked  correctly

Type: Bug Fix
Issue: Bug 34696
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-01-03 15:10:25 +08:00
meseraph cc34b5f0ea mapped pool1d 2022-12-30 10:52:28 +08:00
Chen Xin aa0b474c19 Added a case for fc 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-30 10:34:21 +08:00
Chen Xin c1f8a959af Fixed bug for pad_v2 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-30 10:19:03 +08:00
Chen Xin 0e211c8efd Fixed (groupd)conv2d layout infer bug 
And added a weight_as_input case to test

Type: Bug Fix

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:20:56 +08:00
Feiyue Chen ac4517b5c1 Added EmbeddingLookup 4d support internal 
Added EmbeddingLookup internal support for 4d lut input

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:09:19 +08:00
Feiyue Chen 06b88e7940 Fixed nn_params in groupconv2d 
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:08:14 +08:00
Feiyue Chen c6919248e1 fixed groupconv2d params in internal 
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-16 15:04:54 +08:00
Chen Xin 7582b57edc Added pad_v2 & pad_v2 layout infer 
And added 4 rank case

Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-12-16 15:03:58 +08:00
Feiyue Chen 8d8f4b6e68 Added EmbeddingLookup & deprecate LshProjection 
Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-05 09:59:56 +08:00
Qin.Chen 13da73bbe3 Fix maxpoolgrad, hide unused pool value output 
Type: Bug Fix
 2022-12-01 15:49:38 +08:00
Feiyue Chen b7478f7872 Added invalidate handle marco 
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 15:37:33 +08:00
Feiyue Chen f7b49ae4e2 Modified README.md about rnn&lstm 
Changed status of UnidirecitonalRnn&BidirectionalRnn
Changed status and internal op of BidirectionalLstm

Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 10:56:48 +08:00
Feiyue Chen dd7cd2504c Added HashtableLookup Op 
Added HashtableLookup Op and unit test

Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-12-01 10:55:21 +08:00
Feiyue Chen c231c54a66 Fixed BidirectionalSequenceRnn bugs 
Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified  copyright and log message

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-28 09:45:50 +08:00
Feiyue Chen 05a1c561af Added layout_inference for UnidirectionalRnn 
Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-23 20:58:00 +08:00
Qin.Chen 8cd5bd93ce Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now. 2022-11-22 21:39:02 +08:00
Tang d723ffaf51 fix typo for graph_test.cc 2022-11-22 21:37:40 +08:00
Chen Xin 545d677160 diabled a failed case 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-22 21:36:41 +08:00
Chen Xin 9fe7b955e5 Fixed average pool layout infer 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-16 13:34:31 +08:00
meseraph 883334e1bb add rnn 2022-11-16 13:33:39 +08:00
Feiyue Chen 11fd278d7a Fixed BidirectionalSequenceLSTM bug 
Fixed input error of  the backward direction
Fixed golden error of unit test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-16 13:31:23 +08:00
Kee 4db479ece4 Set RNN internal dtype 
Init RNN internal dtype to avoid the
internal FC OP to go to the CPU path

Type:Code Improvement

Signed-off-by: Kee <xuke537@hotmail.com>
 2022-11-14 09:39:27 +08:00
Feiyue Chen b53fd14375 Update x86_64_linux/include for 22Q3 
update prebuilt-sdk/x86_64_linux/include
update VERSION file

Type:  Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-11 18:22:26 +08:00
Chen Xin 6816a0188a Added minimum unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:03:46 +08:00
Chen Xin 8867c8de35 Fixed roi_align golden mismatch error 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-11-11 18:02:36 +08:00
zhouheng.zheng 25c38d45e1 add custom op in lenet test 2022-10-28 17:43:01 +08:00
Feiyue Chen fde6d799ae Fixed multi_device compiling error in gcc 12 
fixed mismatched allocation error in  multi_device.cc

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:36:13 +08:00
Feiyue Chen 922d10696d Update prebuilt-sdk for 22Q3 release 
Update prebuilt-sdk for 22Q3 release

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Feiyue Chen ed162d0176 Update internal for 22Q3 release 
update internal to commit-id: e2b0fde631fce349e0e3ad42b2a4d40ce7634a97

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-24 15:34:53 +08:00
Feiyue Chen 7baf8c307f Fixed tensorflow version in CI 
modify fetched tensorflow version to v2.10.0

Type: Bug Fix

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-10-19 18:04:52 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-10-08 21:42:02 +08:00
Feiyue Chen a038df2a84 added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429 2022-10-08 14:47:07 +08:00
Chen Xin 20db77ee61 Added two cases in strided_slice 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-29 20:24:09 +08:00
Chen Xin 535c9da867 Fixed bug when input's index is not 0 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 16:48:16 +08:00
Chen Xin 4c6299e7fd Added two reduce layout infer unittest 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-28 09:37:38 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00
Feiyue Chen 264e491d2a added cumsum op & added handle api after BindInput 2022-09-26 14:27:48 +08:00
Feiyue Chen 9cb37b920f added MaxPool3d op 2022-09-26 13:32:56 +08:00
Feiyue Chen 8b8d09aea3 added Rcp op & modified test_utils 2022-09-22 12:15:02 +08:00
Feiyue Chen 1b07b022e2 added sign & softsign 2022-09-20 22:49:45 +08:00
Feiyue Chen f4d5e170de added & modified copyright of some files 2022-09-20 22:47:33 +08:00
Feiyue Chen 84b464ee8b Update README.md 2022-09-20 22:47:33 +08:00