821864a582
Fixed IExecutable object not bind with DeviceID ( #624 )
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If Executable object doesn't bind with a concrete DeviceID,
it will go first device by default.
When run multi executable with multi device, the behavior is not
expected. Fixed by attach device id with CompileOption.
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2023-07-24 22:45:54 +08:00
315adcf076
Integrate api trace into tim-vx source as an experimental feature. ( #623 )
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* Add support for different input dtype of MaxPoolGrad.
Type: Code improvement
* Integrate api trace into tim-vx source code, as part of experimeantal.
Type: New Feature
2023-07-19 18:40:48 +08:00
0885a0d797
Remove confusing comment in depthwise conv test ( #621 )
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Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-07-17 09:43:34 +08:00
62c6b6560c
Added axis param for TopK ( #610 )
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Topk support specifying dimensions with later internal ovxlib
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-07-12 09:54:07 +08:00
ea8046ec9c
Added roi_align layoutinfer & cases ( #615 )
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* Added roi_align layoutinfer & cases
Type: New feature
Signed-off-by: Chen <jack.chen@verisilicon.com>
* Update instancenorm op spec .json
Type: bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
* Added roi_pool layoutinfer & fixed case bug
Type: new feature
Signed-off-by: Chen <jack.chen@verisilicon.com>
---------
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-07-08 23:39:56 +08:00
33f3a4f176
Enable float16 bias convolution model runs on NN ( #612 )
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Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver
Caution: Clang version requires minimum 15.0
Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-30 09:41:28 +08:00
34812fe40e
Added case for gather ( #599 )
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-06-26 09:15:08 +08:00
75882d4195
Added new_axis_mask param for stridedslice ( #600 )
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Add another constructor for stridedslice when new_axis_mask is set
The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-25 09:24:41 +08:00
fbfbdd7c83
Added axis support for layernorm ( #602 )
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Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-15 21:45:46 +08:00
aa7b3a6f8f
Added api json for each op to support acuity ( #596 )
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Record constructor form of each operation as a json file to support acuity to call
timvx op
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-02 07:51:10 +08:00
ea8adc456a
fixed instance norm bug & add its layoutinfer ( #593 )
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Type: Bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-31 12:55:42 +08:00
4f92e58155
optimization for tiny_yolov4 ( #591 )
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Type: code improvment
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-23 14:28:47 +08:00
51faf286c2
Fixed LayerNormalization eps bug ( #589 )
2023-05-22 14:13:44 +08:00
3f83db534d
Added missed ops include header ( #584 )
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Include cumsum, mod, maxpool3d, grucell, UnidirectionalSequanceGRU header file in
ops.h
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-05-16 15:59:16 +08:00
3c372dd646
Refine UnidirectionalGRU and GRUCell ( #587 )
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Refine unidirectional_gru and gru_cell code to avoid including ovxlib files
in header of some op
Introduce TranslateToVsibool function to support above code refinement
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-05-15 16:44:51 +08:00
b81f7979fa
Reload "==" operator for quantizations of two tensor ( #583 )
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Reload operator "==" to check two quantization same or not
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-05-10 17:58:30 +09:00
1543efe098
Add some tensor dtype convert APIs ( #576 )
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For pre/post process.
Type: Code Refine
Co-authored-by: wangqian <wangqian@CNCDD9444.verisilicon.com>
2023-04-27 09:04:39 +08:00
27890719b6
Support remote platform by gRPC ( #561 )
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* Support remote platform by gRPC
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2023-03-28 09:51:23 +08:00
e49f67b840
Remove tensor GetDataRef api ( #569 )
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Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
2023-03-23 21:35:30 +08:00
d778dfb82d
update copyright information
2023-01-20 12:49:48 +08:00
20f759e58a
fix depth2space mode enum
2023-01-17 22:44:44 +08:00
cc34b5f0ea
mapped pool1d
2022-12-30 10:52:28 +08:00
7582b57edc
Added pad_v2 & pad_v2 layout infer
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And added 4 rank case
Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-16 15:03:58 +08:00
8d8f4b6e68
Added EmbeddingLookup & deprecate LshProjection
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Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-05 09:59:56 +08:00
13da73bbe3
Fix maxpoolgrad, hide unused pool value output
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Type: Bug Fix
2022-12-01 15:49:38 +08:00
dd7cd2504c
Added HashtableLookup Op
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Added HashtableLookup Op and unit test
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-01 10:55:21 +08:00
8cd5bd93ce
Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now.
2022-11-22 21:39:02 +08:00
883334e1bb
add rnn
2022-11-16 13:33:39 +08:00
11fd278d7a
Fixed BidirectionalSequenceLSTM bug
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Fixed input error of the backward direction
Fixed golden error of unit test
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-16 13:31:23 +08:00
3fed6d6757
fixed bug when broadcast dimensions is negative
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-10-08 21:42:02 +08:00
72f2c5b69e
Supported composed layout infer & added unit test
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Fixed fc layout infer in rnncell layout infer
2022-09-26 14:29:46 +08:00
1802e558ad
modified cumsum header && resolve conflict in README.md
2022-09-26 14:27:48 +08:00
264e491d2a
added cumsum op & added handle api after BindInput
2022-09-26 14:27:48 +08:00
9cb37b920f
added MaxPool3d op
2022-09-26 13:32:56 +08:00
8b8d09aea3
added Rcp op & modified test_utils
2022-09-22 12:15:02 +08:00
1b07b022e2
added sign & softsign
2022-09-20 22:49:45 +08:00
f4d5e170de
added & modified copyright of some files
2022-09-20 22:47:33 +08:00
6099022f00
added Mod op & Mod unit test
2022-09-20 22:47:33 +08:00
9b13b6f677
Replace name direct_map_op with builtin_op
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-19 10:21:19 +08:00
113c3722cb
supported int16 dfp quantization & added conv2d unit test
2022-09-15 22:15:22 +08:00
95401036ab
fixed some errs on gcc12
2022-09-15 21:26:43 +08:00
e9771746ba
Fix error in feature compatiable guard
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-09-05 15:05:50 +08:00
9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable ( #471 )
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Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-09-01 18:56:49 +08:00
f6121140b0
Mapped unidirectional gru & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-31 09:27:05 +08:00
1c640c6f10
Mapped bidirectional lstm & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-22 10:42:05 +08:00
5482760ba2
include Topk op's header file
2022-08-15 06:29:55 +08:00
944fdfad8f
Mapped GRUCell & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-11 20:34:19 +08:00
9a28ff5758
Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2022-08-08 16:50:25 +08:00
3663a99e0f
Fixed param compute bug for lrn
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-04 21:35:59 +08:00
6d47ee3ac1
Expose hw feature : isClOnly()
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Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
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