Kainan Cha
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c46904c339
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Add op support for Deconv2d
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
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2021-02-26 09:54:01 +08:00 |
Jiang Bo
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0dbaae19c5
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Link whole archive of tim_internal
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-02-25 15:45:35 +08:00 |
Zongwu.Yang
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8082c43317
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Fix cmake build error
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
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2021-02-24 19:06:54 +08:00 |
xiang.zhang
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9d44b4477b
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Added NBG support
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
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2021-02-22 11:38:21 +08:00 |
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Zongwu.Yang
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c5e16157a6
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Update linking style as static linking for sample
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
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2021-02-08 14:47:37 +08:00 |
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Zongwu.Yang
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5108598fd5
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Add Cmake build for tim-vx
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
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2021-02-02 10:04:47 +08:00 |
yuenan.li
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bd4d277ac1
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Support multiply attribute for tensor spec
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-02-01 14:10:03 +08:00 |
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yuenan.li
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44af63b9e9
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[NNRT-811]Map Slice
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-01-22 14:32:43 +08:00 |
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yuenan.li
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0e422b1e6a
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Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-01-19 16:44:43 +08:00 |
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Jiang Bo
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90b7a6fc32
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Rename Op 'Permute' to 'Transpose'
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-12 11:21:51 +08:00 |
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Jiang Bo
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7972af0697
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Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-11 18:27:48 +08:00 |