Feiyue Chen
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1802e558ad
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modified cumsum header && resolve conflict in README.md
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2022-09-26 14:27:48 +08:00 |
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Feiyue Chen
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264e491d2a
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added cumsum op & added handle api after BindInput
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2022-09-26 14:27:48 +08:00 |
liyuenan
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e2180a6341
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Support that op's all inputs are constant (#264)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
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2022-01-14 12:34:38 +08:00 |
chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
xiang.zhang
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e27e15925c
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Add unidirectional sequence lstm support
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
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2021-08-09 13:43:33 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
zhao.xia
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37f686c34d
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Remove DownScaleSizeRounding type
Use RoundType instead of DownScaleSizeRounding.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
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2021-05-25 16:48:50 +08:00 |
Zongwu.Yang
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77b801a590
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Add layout inference feature (#34)
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
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2021-05-08 09:29:47 +08:00 |
Jiang Bo
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7972af0697
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Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-11 18:27:48 +08:00 |