Commit Graph

383 Commits

Author SHA1 Message Date
liyuenan e2180a6341
Support that op's all inputs are constant (#264)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2022-01-14 12:34:38 +08:00
Antkillerfarm 36e6afa567
add alpha & beta parameters for HardSigmoid (#265) 2022-01-13 14:17:19 +08:00
Kainan Cha fe91e7f13d
Update README.md
Add framework support for Paddle-Lite and OpenCV
2022-01-12 14:39:43 +08:00
Antkillerfarm 9813a5da9a
add vxc binary for internal ops (#255)
cmake -DUSE_VXC_BINARY=1 -DVCCOMPILER_PATH=<vcCompiler path> -DGPU_CONFIG_FILE=<gpu config file> ..
2022-01-12 11:04:49 +08:00
Zongwu.Yang 4229ad88b3
support conv3d (#238)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2022-01-11 14:13:15 +08:00
Sven ff25226adb
[Internal] support prebuilt kernel into shared library (#260)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-01-11 11:45:29 +08:00
Sven c1ed45150d
Added strided_slice test case with 5D-tensor (#261)
test case can be found
    https://github.com/VeriSilicon/TIM-VX/issues/213

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-01-10 17:06:26 +08:00
Sven 58d2c0dedc
Fix GCC5 build error (#259)
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-01-10 01:56:36 +08:00
Sven ed47c5c24c
Update internal to 1.1.37_preview (#254)
* update internal to V1.1.37

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update VSimulator V6.4.9 for linux x86_64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-01-10 01:56:00 +08:00
liyuenan 7c63ba621e
Map OneHot & unit test (#258)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2022-01-05 22:04:49 +08:00
Goose Bomb 8e4ab68213
Fix warnings relating to inheritance (#256)
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance
2022-01-04 14:35:17 +08:00
chxin66 eecbe264b6
Add a unit_test for div_uint8 (#251)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-12-30 13:31:30 +08:00
liyuenan 6275f84575
Fix the conflict for previous two commits (#253)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-29 15:38:42 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250)
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-29 11:06:28 +08:00
Zongwu.Yang aed3a48248
Add layout inference and unit test for BatchNorm (#243)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-12-22 09:47:57 +08:00
Sven e42faad710
Fix build issue if 40BIT_VA enabled (#240)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-12-17 15:00:14 +08:00
Sven 321a53fd2a
Support single static-library for libtim-vx.a (#237)
Fix external ovxlib build failure, and change install dir to CMAKE_INSTALL_LIBDIR

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-15 22:23:32 +08:00
liyuenan 2c38f89d06
Catch the correct output when output has consumer (#239)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-15 09:54:54 +08:00
chxin66 1f85d21558
mapped signal frame & unit test (#234)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-12-09 10:33:40 +08:00
chxin66 dc31091db5
mapped groupedconv1d & unit test (#233)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-12-06 19:20:13 +08:00
Zongwu.Yang bd496219c8
Add quantize, dequantize, requantize test (#232)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-12-02 15:40:41 +08:00
Antkillerfarm b38bd41933
add DataLayout::IcOcWH for TVM usage (#231) 2021-11-30 21:33:14 +08:00
Antkillerfarm e001d53ddf
remove 64bit data type from doc (#230) 2021-11-29 11:02:44 +08:00
Sven 62a33ecfde
Install libtim-vx.so to lib64 if build for aarch64 (#225)
* Install libtim-vx.so to lib64 if build for aarch64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-24 15:18:29 +08:00
Sven bc42f7987c
Fix build if lowlevel driver doesn't support DMABuffer fd (#224)
* Fix build if lowlevel driver doesn't support DMABuffer fd

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-23 11:34:03 +08:00
Sven 9b115ca25b
Add VIM3 information (#223)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-22 12:00:45 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-11-21 22:46:20 +08:00
Zihao Mu 8ea83f137c
Update README.md (#222) 2021-11-21 13:00:24 +08:00
Zongwu.Yang c90efe70c5
Refine Lite API (#221)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-11-19 20:30:26 +08:00
Sven 0ca4970d72
Add instruction for build with local gtest source (#219)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-17 11:03:48 +08:00
Sven 31c716b271
Update README.md (#218) 2021-11-15 12:18:03 +08:00
Sven e81cba0526
Update license header (#216)
* Update license for nbg_parser.c

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update license for headers

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-12 10:07:28 +08:00
Sven 81e28e8b0d
Update license for nbg_parser.c (#215)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-11 14:07:10 +08:00
chxin66 516a914c73
Mapped Erf operation & unit tests (#211)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-11-10 20:07:06 +08:00
Zongwu.Yang d019a76db5
Add function for lite driver handle (#209)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
2021-11-10 20:05:31 +08:00
Sven 4b5fcf3c64
Add reference board information (#212)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-10 11:10:00 +08:00
Antkillerfarm 214cbe5874
add Global Pool2d & Adaptive Pool2d (#210) 2021-11-09 20:25:02 +08:00
Sven 23ec5e9da5
Refine op status (#208)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-11-09 13:10:09 +08:00
Zhouheng Zheng 68b5acbe7c
Fix layout inference bug for resize layer(#205)
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
2021-11-04 19:13:21 +08:00
Kee c9086e0afe
Update Div OP - add scale param (#203)
Update Div OP - add scale param
2021-11-04 10:44:52 +08:00
chxin66 e4cc133d36
Add SVDF support - only FLOAT32 supported
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2021-10-29 16:19:15 +08:00
Kainan Cha f5881c6fa5
Add dispatch_workflow to CI action (#198)
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-22 11:45:04 +08:00
Kainan Cha 5071ba9cd4
Add TIM-VX Architecture overview (#197)
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>

Co-authored-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-21 19:31:41 +08:00
Antkillerfarm 271360f89d
improve Readme.md (#196) 2021-10-21 19:18:42 +08:00
Kainan Cha 2243afcb6e Fix CI badge
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-20 17:20:47 +08:00
Kainan Cha 300850a8fa Add bazel unit test CI
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-20 17:15:33 +08:00
Kainan Cha e111c35d9f Fix bazel BUILD
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-20 16:18:48 +08:00
Kainan Cha 99db6ab69d Remove bazelversion
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-10-15 16:49:55 +08:00
Sven f8846e701e
Update CMakeLists.txt (#187)
Enable build tim-vx as dynamic-library by default will be more friendly for other repo such as tflite-vx-delegate.
2021-10-12 19:50:55 +08:00