Chen Xin
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9b13b6f677
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Replace name direct_map_op with builtin_op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2022-09-19 10:21:19 +08:00 |
chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
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chxin66
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dc31091db5
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mapped groupedconv1d & unit test (#233)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-06 19:20:13 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
zhao.xia
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0ed1e8947f
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Add new APIs for conv, deconv and fc
The new apis remvoe weights, oc_count and ksize.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
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2021-06-07 21:48:13 +08:00 |
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zhao.xia
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be0a566042
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Add map for Conv1D
Convolution 1D operation, support float32, int8, int16, uint8.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
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2021-05-21 12:46:56 +08:00 |