Chen Xin
|
9b13b6f677
|
Replace name direct_map_op with builtin_op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
|
2022-09-19 10:21:19 +08:00 |
chxin66
|
242a6bd05a
|
Add pad value for grouped_conv1d (#292)
https://github.com/VeriSilicon/TIM-VX/issues/284
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
|
2022-02-21 19:11:36 +08:00 |
|
chxin66
|
cea11422b8
|
Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
|
2021-12-29 11:08:24 +08:00 |
|
chxin66
|
dc31091db5
|
mapped groupedconv1d & unit test (#233)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
|
2021-12-06 19:20:13 +08:00 |