Chen Xin
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9b13b6f677
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Replace name direct_map_op with builtin_op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2022-09-19 10:21:19 +08:00 |
MESeraph
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eab0d807a6
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Added Ceil & unit test (#381)
* Added Ceil & unit test
* Added Round & Unit test
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2022-05-05 17:11:31 +08:00 |
chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
jing.tang
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3339135c82
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
Kainan Cha
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d92e08e502
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Add support for Cast and Floor operation
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-05-11 18:45:28 +08:00 |
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Kainan Cha
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165b3fcf8f
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Minor clean up
Fix typos and move functions into appropriate files
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-04-07 13:03:56 +08:00 |
Kainan Cha
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0d7afd9d51
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Minor cleanup
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
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2021-03-19 11:12:12 +08:00 |
Jiang Bo
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7972af0697
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Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-11 18:27:48 +08:00 |