TIM-VX

Author	SHA1	Message	Date
Chen Xin	9b13b6f677	Replace name direct_map_op with builtin_op Signed-off-by: Chen Xin <jack.chen@verisilicon.com>	2022-09-19 10:21:19 +08:00
liyuenan	fe31a47bf9	enable no bias in FC layout inference (#294 ) Signed-off-by: yuenan.li <yuenan.li@verisilicon.com> Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>	2022-02-21 19:09:38 +08:00
chxin66	cea11422b8	Added RNNCell & unit test (#249 ) Signed-off-by: Chen Xin <jack.chen@verisilicon.com> Co-authored-by: Chen Xin <jack.chen@verisilicon.com>	2021-12-29 11:08:24 +08:00
Goose Bomb	914e280209	Refactor CMake build system (#184 ) * Remove unnecessary compiler flags * Refactor CMakeLists.txt * Tweak CMakeLists.txt for libtim_internal * Tweak CMakeLists.txt for libtim-vx * Make TIM_VX_ENABLE_TEST defaults to OFF * Eliminate usage of include_directories * Fix CI unit test	2021-10-12 10:44:49 +08:00
yuenan.li	29f1efc492	add API 'Clone' to tim_vx op and support default layout inference Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>	2021-07-06 12:29:18 +08:00
liyuenan	cc3b8c1fe0	Support layout inference for FC and Resize (#45 ) Signed-off-by: yuenan.li <yuenan.li@verisilicon.com> Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>	2021-05-15 22:42:11 +08:00