Chen Xin
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9b13b6f677
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Replace name direct_map_op with builtin_op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2022-09-19 10:21:19 +08:00 |
chxin66
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0dc38eac2e
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Added unit test for maxpool (#361)
https://github.com/VeriSilicon/TIM-VX/issues/318
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2022-04-13 22:16:47 +08:00 |
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chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
Antkillerfarm
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214cbe5874
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add Global Pool2d & Adaptive Pool2d (#210)
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2021-11-09 20:25:02 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
zhao.xia
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bd9c5df70a
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Add pad parameter to pool2d
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
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2021-06-03 16:28:42 +08:00 |
jing.tang
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3339135c82
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
Zongwu.Yang
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77b801a590
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Add layout inference feature (#34)
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
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2021-05-08 09:29:47 +08:00 |
zhengzhouheng
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c8b0180e7a
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fix the bug of pooling layer output shape mismatch
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2021-02-24 10:15:24 +08:00 |
Jiang Bo
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7972af0697
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Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-11 18:27:48 +08:00 |