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15 Commits

Author SHA1 Message Date
Chen Feiyue af50cc5e3f
Added general Float16 support (#631) 
Added Float16 type definition from third-party
Refine float16 bias handlling in conv2d
Refine float16 case in conv2d
Caution: Headers of float16 only be included when build unit_test

Type: New Feature

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-08-12 10:04:16 +08:00
Chen Feiyue 0885a0d797
Remove confusing comment in depthwise conv test (#621) 
Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv

Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-07-17 09:43:34 +08:00
Chen Feiyue 33f3a4f176
Enable float16 bias convolution model runs on NN (#612) 
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver

Caution: Clang version requires minimum 15.0

Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744

Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2023-06-30 09:41:28 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-14 12:34:38 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
zhao.xia 0ed1e8947f Add new APIs for conv, deconv and fc 
The new apis remvoe weights, oc_count and ksize.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-07 21:48:13 +08:00
jing.tang ebad62ab02 [NNRT-1111] add memory layout for doc 2021-06-01 16:59:55 +08:00
jing.tang 3339135c82 add docs for ops 2021-05-21 18:39:59 +08:00
jing.tang a85fe89cf6 add docs for ops 2021-05-21 18:39:59 +08:00
Zongwu.Yang b38cad9f1d
Add data layout for kernel to support TVM conv2d (#40) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-14 14:00:02 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-11 18:27:48 +08:00