90a52ea6c9
Add support for Mish, SoftRelu and HardSigmoid
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Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-31 12:00:02 +08:00
f92a5de68b
Set Graph Version during in Compile()
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-03-29 17:11:06 +08:00
c569555f1f
Use FCL2 instead of FCL which supports axis
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Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-03-29 17:08:22 +08:00
c141416238
Update internal to REL/v1.1.30.2
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SHA: 2e64046f
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
2021-03-29 16:25:12 +08:00
b5f2666e92
Map Select
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-03-25 17:27:04 +08:00
0d7afd9d51
Minor cleanup
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Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-19 11:12:12 +08:00
cfc70c48df
Use auto shape for virtual tensors
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Use auto shape for virtual tensors so that TIM-VX can
perform its internal shape inference and graph
optimizations.
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-18 14:24:10 +08:00
b6f0ffaef6
Fix Mutliply API
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Internal ops require a scale parameter to be initialized
to 1.0f.
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-17 17:56:11 +08:00
f79aac314c
Fix bug in tensor attribute setting
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-03-17 16:50:45 +08:00
8f1c33ea83
add README.md for op support
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-03-16 11:46:57 +08:00
def53f4b5c
Update internal to REL/v1.1.30
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Commit: 6ccb425e
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-02-26 17:05:14 +08:00
c46904c339
Add op support for Deconv2d
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Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
2021-02-26 09:54:01 +08:00
0dbaae19c5
Link whole archive of tim_internal
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Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-02-25 15:45:35 +08:00
8082c43317
Fix cmake build error
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Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
2021-02-24 19:06:54 +08:00
9d44b4477b
Added NBG support
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2021-02-22 11:38:21 +08:00
c5e16157a6
Update linking style as static linking for sample
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Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
2021-02-08 14:47:37 +08:00
5108598fd5
Add Cmake build for tim-vx
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Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
2021-02-02 10:04:47 +08:00
bd4d277ac1
Support multiply attribute for tensor spec
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-02-01 14:10:03 +08:00
44af63b9e9
[NNRT-811]Map Slice
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-01-22 14:32:43 +08:00
0e422b1e6a
Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-01-19 16:44:43 +08:00
90b7a6fc32
Rename Op 'Permute' to 'Transpose'
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Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-12 11:21:51 +08:00
7972af0697
Initial Commit for VERSION 1.1.28
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Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
2021-01-11 18:27:48 +08:00
Kainan Cha
Kainan Cha
yuenan.li
Jiang Bo
Zongwu.Yang
xiang.zhang