2 Commits

Author	SHA1	Message	Date
Sven	86fcb0d0e0	Fix build error with gcc 6.2.0 (#282) ... Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>	2022-01-27 11:42:12 +08:00
Sven	c1ed45150d	Added strided_slice test case with 5D-tensor (#261) ... test case can be found https://github.com/VeriSilicon/TIM-VX/issues/213 Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2022-01-10 17:06:26 +08:00