chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
Chen Xin
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633075f689
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delete Non-approximate option, recommend to use
the approximate option
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2021-09-07 22:44:57 +08:00 |
Antkillerfarm
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fa930678ea
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add Programming_Guide.md & Operators.md (#157)
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2021-08-24 12:42:46 +08:00 |
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chxin66
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5e09e98c1a
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Add Gelu support for tim::vx (#153)
* Add map for Gelu
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2021-08-17 20:37:12 +08:00 |
jing.tang
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a364c3eafb
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add Swish op
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2021-08-16 19:30:14 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
Kainan Cha
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39bd5ddd32
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Add support for Linear Activation
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-06-02 17:10:57 +08:00 |
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jing.tang
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3339135c82
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
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jing.tang
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a85fe89cf6
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
Kainan Cha
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90a52ea6c9
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Add support for Mish, SoftRelu and HardSigmoid
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
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2021-03-31 12:00:02 +08:00 |
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Kainan Cha
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0d7afd9d51
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Minor cleanup
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
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2021-03-19 11:12:12 +08:00 |
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yuenan.li
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0e422b1e6a
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Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-01-19 16:44:43 +08:00 |
Jiang Bo
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7972af0697
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Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-11 18:27:48 +08:00 |