chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
zhao.xia
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0ed1e8947f
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Add new APIs for conv, deconv and fc
The new apis remvoe weights, oc_count and ksize.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
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2021-06-07 21:48:13 +08:00 |
jing.tang
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ebad62ab02
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[NNRT-1111] add memory layout for doc
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2021-06-01 16:59:55 +08:00 |
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jing.tang
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3339135c82
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
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jing.tang
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a85fe89cf6
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
Zongwu.Yang
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b38cad9f1d
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Add data layout for kernel to support TVM conv2d (#40)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
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2021-05-14 14:00:02 +08:00 |
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Zongwu.Yang
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77b801a590
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Add layout inference feature (#34)
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
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2021-05-08 09:29:47 +08:00 |
Jiang Bo
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7972af0697
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Initial Commit for VERSION 1.1.28
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
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2021-01-11 18:27:48 +08:00 |