chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
yuenan.li
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29f1efc492
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add API 'Clone' to tim_vx op and support default layout inference
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-07-06 12:29:18 +08:00 |
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yuenan.li
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1f08618403
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Supprt layout inference for Operations
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
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2021-06-02 00:53:11 +08:00 |
jing.tang
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a85fe89cf6
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add docs for ops
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2021-05-21 18:39:59 +08:00 |
xiang.zhang
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b1b7eadefc
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Add group parameter for deconv API
Limitation: only support depthwise deconvolution
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
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2021-05-20 06:15:28 +08:00 |
Kainan Cha
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c46904c339
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Add op support for Deconv2d
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
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2021-02-26 09:54:01 +08:00 |