chxin66
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cea11422b8
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Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-29 11:08:24 +08:00 |
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chxin66
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1f85d21558
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mapped signal frame & unit test (#234)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
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2021-12-09 10:33:40 +08:00 |
Chen Xin
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6f2e92ffa6
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Add shuffle_channel support & test for tim::vx
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
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2021-09-07 22:44:57 +08:00 |