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150 Commits

Author SHA1 Message Date
meseraph 883334e1bb add rnn 2022-11-16 13:33:39 +08:00
Feiyue Chen 11fd278d7a Fixed BidirectionalSequenceLSTM bug 
Fixed input error of  the backward direction
Fixed golden error of unit test

Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
 2022-11-16 13:31:23 +08:00
Chen Xin 3fed6d6757 fixed bug when broadcast dimensions is negative 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-10-08 21:42:02 +08:00
Chen Xin 72f2c5b69e Supported composed layout infer & added unit test 
Fixed fc layout infer in rnncell layout infer
 2022-09-26 14:29:46 +08:00
Feiyue Chen 1802e558ad modified cumsum header && resolve conflict in README.md 2022-09-26 14:27:48 +08:00
Feiyue Chen 264e491d2a added cumsum op & added handle api after BindInput 2022-09-26 14:27:48 +08:00
Feiyue Chen 9cb37b920f added MaxPool3d op 2022-09-26 13:32:56 +08:00
Feiyue Chen 8b8d09aea3 added Rcp op & modified test_utils 2022-09-22 12:15:02 +08:00
Feiyue Chen 1b07b022e2 added sign & softsign 2022-09-20 22:49:45 +08:00
Feiyue Chen f4d5e170de added & modified copyright of some files 2022-09-20 22:47:33 +08:00
Feiyue Chen 6099022f00 added Mod op & Mod unit test 2022-09-20 22:47:33 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-09-19 10:21:19 +08:00
Feiyue Chen 113c3722cb supported int16 dfp quantization & added conv2d unit test 2022-09-15 22:15:22 +08:00
Feiyue Chen 95401036ab fixed some errs on gcc12 2022-09-15 21:26:43 +08:00
xiang.zhang e9771746ba Fix error in feature compatiable guard 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-05 15:05:50 +08:00
Sven 9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable (#471) 
Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-09-01 18:56:49 +08:00
Chen Xin f6121140b0 Mapped unidirectional gru & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-31 09:27:05 +08:00
Chen Xin 1c640c6f10 Mapped bidirectional lstm & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-22 10:42:05 +08:00
qin.chen 5482760ba2 include Topk op's header file 2022-08-15 06:29:55 +08:00
Chen Xin 944fdfad8f Mapped GRUCell & unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-11 20:34:19 +08:00
yuenan.li 9a28ff5758 Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-08-08 16:50:25 +08:00
Chen Xin 3663a99e0f Fixed param compute bug for lrn 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-08-04 21:35:59 +08:00
ZhangXiang 6d47ee3ac1 Expose hw feature : isClOnly() 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-08-03 09:06:32 +08:00
zhouheng.zheng ecfc8735d9 update nbg format version 2022-07-29 12:40:25 +08:00
qin.chen 9ebddb5452 add op: maxpoolwithargmax2 and maxpoolgrad 2022-07-29 11:11:33 +08:00
Antkillerfarm 32241dc4ad
Rename RoiAlign & RoiPool (#446) 2022-07-29 11:10:25 +08:00
chxin66 9f331ed5ec
Added batch dims in gather (#435) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-07-19 12:33:09 +08:00
MESeraph 11f953b506
Mapped roi_pool & added unit test (#404) 
* Mapped roi_pool & added unit test

* modify roialign/roipool unit test
 2022-05-30 19:57:50 +08:00
chxin66 44cc6f9f09
lstm layout inference & Added unidirectional lstm layout inference (#392) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-29 22:40:43 +08:00
MESeraph 6d0c6b01b5
modify GatherElements (#406) 2022-05-29 22:25:14 +08:00
chxin66 1b4c30e572
Mapped roi_align & added unit test (#402) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-27 16:34:48 +08:00
Dahan Gong f8741b4704
feat(tensor): support external buffer when creating input/output tensors (#389) 
* support external buffer when creating input/output tensors

* feat(tensor): add new map/unmap APIs
 2022-05-18 23:38:26 +08:00
Antkillerfarm b3677305c4
add GetElementNum/GetElementByteSize/GetByteSize for TensorSpec (#393) 2022-05-13 14:29:25 +08:00
chxin66 0d8ac3dc2b
Added gather_elements & unit test (#363) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-10 09:55:50 +08:00
MESeraph eab0d807a6
Added Ceil & unit test (#381) 
* Added Ceil & unit test

* Added Round & Unit test
 2022-05-05 17:11:31 +08:00
chxin66 7a8ae32f73
Added topk & unit test (#384) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-05-05 17:06:39 +08:00
Antkillerfarm dbb3631d4e
rename CopyTensorToData to CopyDataFromTensor to align name of tim::vx::Tensor (#373) 2022-04-24 13:36:51 +08:00
Antkillerfarm b916e1301a
Add Broadcast op (#365) 2022-04-18 15:45:15 +08:00
chxin66 96dedc1453
Added selu & celu & unit test (#366) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-18 14:35:29 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 479fc576ae
Suported specifying CRD_mode & DCR_mode in depthtospace (#362) 
https://github.com/VeriSilicon/TIM-VX/issues/304

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:53:32 +08:00
chxin66 0dc38eac2e
Added unit test for maxpool (#361) 
https://github.com/VeriSilicon/TIM-VX/issues/318

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 22:16:47 +08:00
chxin66 93f20429ea
Fixed layout inference bug for stride_slice (#329) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:12:37 +08:00
chxin66 c033cfc582
Fixed compiler fail for elu (#358) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 18:42:50 +08:00
chxin66 e8ca6b8ee3
Added param step for slice & added unit test (#352) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 15:42:58 +08:00
chxin66 d0af7ae8df
Support alpha in elu (#354) 
https://github.com/VeriSilicon/TIM-VX/issues/305

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-11 19:04:30 +08:00
lucklee 70d2f410a8
support virtual vip devices (#331) 2022-04-06 13:05:38 +08:00
chxin66 1ca89d2ffa
Add layout inference & layout test for stack (#337) 
* Added layout inference & layout test for stack

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-06 13:01:41 +08:00
Sven 171abb0f1b
Revert "composed Dense & added unit test (#312)" (#340) 
This reverts commit f2e71a3deb.
 2022-03-31 18:37:45 +08:00
chxin66 f2e71a3deb
composed Dense & added unit test (#312) 
if shape is 3D or larger, implement it as reshape + fc + reshape

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-03-25 10:49:39 +08:00