Kainan Cha
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e111c35d9f
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Fix bazel BUILD
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-10-20 16:18:48 +08:00 |
Kainan Cha
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c4543c706f
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Add pthread to avoid static linkage issue (#188)
Add pthread to avoid static linkage issue
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-10-12 13:47:10 +08:00 |
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Kainan Cha
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d7900b9de4
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Add sample to run NBG
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
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2021-09-27 17:21:04 +08:00 |
Jing.Deng
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8d35c4dd7a
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add uint8 quantized unit_test for conv2d
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
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2021-06-07 13:30:43 +08:00 |
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Kainan Cha
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56bd7bf8c8
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Add prebuild support for VIPLite
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-05-14 18:31:08 +08:00 |
zhao.xia
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0a034252c6
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Support tim-lite
Lite module for vip lite driver.
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
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2021-05-14 17:37:35 +08:00 |
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Kainan Cha
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c2e10efb50
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Add support for Reorg
The Reorg implementation is that of YOLOv2.
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
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2021-05-11 10:57:56 +08:00 |
Sven
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a42517fdce
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Align directory name to namespace for layout inference (#38)
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
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2021-05-11 09:46:46 +08:00 |
Zongwu.Yang
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22d423714f
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Optimize permute op for constant tensor (#37)
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
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2021-05-10 23:06:04 +08:00 |
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Zongwu.Yang
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77b801a590
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Add layout inference feature (#34)
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
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2021-05-08 09:29:47 +08:00 |
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Kainan Cha
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01fabba95e
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Rename BUILD.bazel to BUILD
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
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2021-02-26 09:53:32 +08:00 |