TIM-VX

Author	SHA1	Message	Date
chxin66	cea11422b8	Added RNNCell & unit test (#249 ) Signed-off-by: Chen Xin <jack.chen@verisilicon.com> Co-authored-by: Chen Xin <jack.chen@verisilicon.com>	2021-12-29 11:08:24 +08:00
yuenan.li	29f1efc492	add API 'Clone' to tim_vx op and support default layout inference Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>	2021-07-06 12:29:18 +08:00
yuenan.li	1f08618403	Supprt layout inference for Operations Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>	2021-06-02 00:53:11 +08:00
Sven	c3858af4fc	Fix bazel build by warning as error (#58 ) Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2021-05-20 16:23:04 +08:00
Sven	e3b127df50	Add group parameter for deconv API (#51 ) * Add group parameter for deconv API Limitation: only support depthwise deconvolution Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com> * Add single channel case and fix build warning Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2021-05-20 10:56:52 +08:00
xiang.zhang	b1b7eadefc	Add group parameter for deconv API Limitation: only support depthwise deconvolution Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2021-05-20 06:15:28 +08:00
Kainan Cha	c46904c339	Add op support for Deconv2d Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>	2021-02-26 09:54:01 +08:00