TIM-VX

Commit Graph

Author	SHA1	Message	Date
Yunshan	feaf06365b	Refine layout inference (#671 ) * Remove unnecessary compiler flags * Refactor CMakeLists.txt * Tweak CMakeLists.txt for libtim_internal * Tweak CMakeLists.txt for libtim-vx * Make TIM_VX_ENABLE_TEST defaults to OFF * Eliminate usage of include_directories * Fix CI unit test * Fix warnings relating to inheritance * Keep graph output order in layout inference Type: Code Improvement * Fix typos in layout inference Type: Code Improvement --------- authored-by: Xiaoran Weng <Xiaoran.Weng@verisilicon.com>	2023-12-20 21:26:16 +08:00
liyuenan	2c38f89d06	Catch the correct output when output has consumer (#239 ) Signed-off-by: yuenan.li <yuenan.li@verisilicon.com> Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>	2021-12-15 09:54:54 +08:00
Sven	a42517fdce	Align directory name to namespace for layout inference (#38 ) Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>	2021-05-11 09:46:46 +08:00

Author

SHA1

Message

Date

Yunshan

feaf06365b

Refine layout inference (#671 )

* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance

* Keep graph output order in layout inference

Type: Code Improvement

* Fix typos in layout inference

Type: Code Improvement

---------

authored-by: Xiaoran Weng <Xiaoran.Weng@verisilicon.com>

2023-12-20 21:26:16 +08:00

liyuenan

2c38f89d06

Catch the correct output when output has consumer (#239 )

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>

2021-12-15 09:54:54 +08:00

Sven

a42517fdce

Align directory name to namespace for layout inference (#38 )

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

2021-05-11 09:46:46 +08:00

3 Commits