Commit Graph

7 Commits

Author SHA1 Message Date
Yunshan feaf06365b
Refine layout inference (#671)
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance

* Keep graph output order in layout inference

Type: Code Improvement

* Fix typos in layout inference

Type: Code Improvement

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authored-by: Xiaoran Weng <Xiaoran.Weng@verisilicon.com>
2023-12-20 21:26:16 +08:00
Tang d778dfb82d update copyright information 2023-01-20 12:49:48 +08:00
Chen Xin 9b13b6f677 Replace name direct_map_op with builtin_op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-19 10:21:19 +08:00
chxin66 f52cb852d6
Fixed transpose layout inference bug (#430)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2022-07-11 09:55:48 +08:00
Sven 4f2991c853
Fixed no-output if transpose is last op and can be optimized (#395)
* Fixed no-output if transpose is last op and can be optimized

If transpose can be erased by layout inference, replace it as a
reshape - input and output have same shape - expect low-level
optimization erase the reshape

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-05-13 16:59:25 +08:00
liyuenan 6275f84575
Fix the conflict for previous two commits (#253)
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-29 15:38:42 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250)
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2021-12-29 11:06:28 +08:00