chxin66 0dc38eac2e Added unit test for maxpool (#361) ... https://github.com/VeriSilicon/TIM-VX/issues/318 Signed-off-by: Chen Xin <jack.chen@verisilicon.com>		2022-04-13 22:16:47 +08:00
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tim	Added unit test for maxpool (#361)	2022-04-13 22:16:47 +08:00