TIM-VX/include
chxin66 1b4c30e572
Mapped roi_align & added unit test (#402)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2022-05-27 16:34:48 +08:00
..
tim Mapped roi_align & added unit test (#402) 2022-05-27 16:34:48 +08:00