chxin66 1ca89d2ffa Add layout inference & layout test for stack (#337) ... * Added layout inference & layout test for stack Signed-off-by: Chen Xin <jack.chen@verisilicon.com>		2022-04-06 13:01:41 +08:00
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tim	Add layout inference & layout test for stack (#337)	2022-04-06 13:01:41 +08:00