TIM-VX/include/tim/vx
chxin66 cea11422b8
Added RNNCell & unit test (#249)
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2021-12-29 11:08:24 +08:00
..
ops Added RNNCell & unit test (#249) 2021-12-29 11:08:24 +08:00
context.h Added NBG support 2021-02-22 11:38:21 +08:00
direct_map_op.h Added RNNCell & unit test (#249) 2021-12-29 11:08:24 +08:00
graph.h Support layout inference for transpose (#250) 2021-12-29 11:06:28 +08:00
operation.h Added RNNCell & unit test (#249) 2021-12-29 11:08:24 +08:00
ops.h Added RNNCell & unit test (#249) 2021-12-29 11:08:24 +08:00
tensor.h support DMAbuffer (#214) 2021-11-21 22:46:20 +08:00
types.h mapped groupedconv1d & unit test (#233) 2021-12-06 19:20:13 +08:00