abstractaccelerator/VexRiscv/sim/murax.cfg

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2022-02-25 19:56:36 +08:00
set _ENDIAN little
set _TAP_TYPE 1234
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# set useful default
set _CPUTAPID 0x10001fff
}
adapter_khz 800
adapter_nsrst_delay 260
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jtag_ntrst_delay 250
set _CHIPNAME fpga_spinal
jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF
target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge -coreid 0 -dbgbase 0xF00F0000
vexriscv readWaitCycles 12
vexriscv cpuConfigFile $MURAX_CPU0_YAML
poll_period 50
init
#echo "Halting processor"
soft_reset_halt
sleep 1000