844 lines
31 KiB
Systemverilog
844 lines
31 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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module soc_top (
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input clk,
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input dbg_rst,
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input rst,
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output jtag_tdo,
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input jtag_tck,
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input jtag_tms,
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input jtag_tdi,
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input jtag_trst_n
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);
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logic nmi_int;
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logic [31:0] reset_vector;
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logic [31:0] nmi_vector;
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logic [31:1] jtag_id;
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logic [31:0] ic_haddr ;
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logic [2:0] ic_hburst ;
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logic ic_hmastlock ;
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logic [3:0] ic_hprot ;
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logic [2:0] ic_hsize ;
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logic [1:0] ic_htrans ;
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logic ic_hwrite ;
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logic [63:0] ic_hrdata ;
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logic ic_hready ;
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logic ic_hresp ;
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logic [31:0] lsu_haddr ;
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logic [2:0] lsu_hburst ;
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logic lsu_hmastlock ;
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logic [3:0] lsu_hprot ;
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logic [2:0] lsu_hsize ;
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logic [1:0] lsu_htrans ;
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logic lsu_hwrite ;
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logic [63:0] lsu_hrdata ;
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logic [63:0] lsu_hwdata ;
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logic lsu_hready ;
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logic lsu_hresp ;
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logic [31:0] sb_haddr ;
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logic [2:0] sb_hburst ;
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logic sb_hmastlock ;
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logic [3:0] sb_hprot ;
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logic [2:0] sb_hsize ;
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logic [1:0] sb_htrans ;
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logic sb_hwrite ;
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logic [63:0] sb_hrdata ;
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logic [63:0] sb_hwdata ;
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logic sb_hready ;
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logic sb_hresp ;
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logic [31:0] trace_rv_i_insn_ip;
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logic [31:0] trace_rv_i_address_ip;
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logic trace_rv_i_valid_ip;
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logic trace_rv_i_exception_ip;
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logic [4:0] trace_rv_i_ecause_ip;
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logic trace_rv_i_interrupt_ip;
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logic [31:0] trace_rv_i_tval_ip;
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logic o_debug_mode_status;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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logic o_cpu_run_ack;
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logic mailbox_write;
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logic [63:0] dma_hrdata ;
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logic [63:0] dma_hwdata ;
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logic dma_hready ;
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logic dma_hresp ;
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logic mpc_debug_halt_req;
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logic mpc_debug_run_req;
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logic mpc_reset_run_req;
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logic mpc_debug_halt_ack;
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logic mpc_debug_run_ack;
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logic debug_brkpt_status;
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int cycleCnt;
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logic mailbox_data_val;
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wire dma_hready_out;
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int commit_count;
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logic wb_valid;
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logic [4:0] wb_dest;
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logic [31:0] wb_data;
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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wire lsu_axi_awvalid;
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wire lsu_axi_awready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;
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wire [31:0] lsu_axi_awaddr;
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wire [3:0] lsu_axi_awregion;
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wire [7:0] lsu_axi_awlen;
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wire [2:0] lsu_axi_awsize;
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wire [1:0] lsu_axi_awburst;
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wire lsu_axi_awlock;
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wire [3:0] lsu_axi_awcache;
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wire [2:0] lsu_axi_awprot;
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wire [3:0] lsu_axi_awqos;
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wire lsu_axi_wvalid;
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wire lsu_axi_wready;
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wire [63:0] lsu_axi_wdata;
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wire [7:0] lsu_axi_wstrb;
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wire lsu_axi_wlast;
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wire lsu_axi_bvalid;
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wire lsu_axi_bready;
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wire [1:0] lsu_axi_bresp;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;
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// AXI Read Channels
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wire lsu_axi_arvalid;
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wire lsu_axi_arready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;
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wire [31:0] lsu_axi_araddr;
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wire [3:0] lsu_axi_arregion;
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wire [7:0] lsu_axi_arlen;
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wire [2:0] lsu_axi_arsize;
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wire [1:0] lsu_axi_arburst;
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wire lsu_axi_arlock;
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wire [3:0] lsu_axi_arcache;
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wire [2:0] lsu_axi_arprot;
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wire [3:0] lsu_axi_arqos;
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wire lsu_axi_rvalid;
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wire lsu_axi_rready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;
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wire [63:0] lsu_axi_rdata;
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wire [1:0] lsu_axi_rresp;
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wire lsu_axi_rlast;
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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wire ifu_axi_awvalid;
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wire ifu_axi_awready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;
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wire [31:0] ifu_axi_awaddr;
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wire [3:0] ifu_axi_awregion;
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wire [7:0] ifu_axi_awlen;
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wire [2:0] ifu_axi_awsize;
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wire [1:0] ifu_axi_awburst;
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wire ifu_axi_awlock;
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wire [3:0] ifu_axi_awcache;
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wire [2:0] ifu_axi_awprot;
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wire [3:0] ifu_axi_awqos;
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wire ifu_axi_wvalid;
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wire ifu_axi_wready;
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wire [63:0] ifu_axi_wdata;
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wire [7:0] ifu_axi_wstrb;
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wire ifu_axi_wlast;
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wire ifu_axi_bvalid;
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wire ifu_axi_bready;
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wire [1:0] ifu_axi_bresp;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;
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// AXI Read Channels
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wire ifu_axi_arvalid;
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wire ifu_axi_arready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;
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wire [31:0] ifu_axi_araddr;
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wire [3:0] ifu_axi_arregion;
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wire [7:0] ifu_axi_arlen;
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wire [2:0] ifu_axi_arsize;
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wire [1:0] ifu_axi_arburst;
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wire ifu_axi_arlock;
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wire [3:0] ifu_axi_arcache;
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wire [2:0] ifu_axi_arprot;
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wire [3:0] ifu_axi_arqos;
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wire ifu_axi_rvalid;
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wire ifu_axi_rready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;
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wire [63:0] ifu_axi_rdata;
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wire [1:0] ifu_axi_rresp;
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wire ifu_axi_rlast;
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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wire sb_axi_awvalid;
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wire sb_axi_awready;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_awid;
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wire [31:0] sb_axi_awaddr;
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wire [3:0] sb_axi_awregion;
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wire [7:0] sb_axi_awlen;
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wire [2:0] sb_axi_awsize;
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wire [1:0] sb_axi_awburst;
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wire sb_axi_awlock;
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wire [3:0] sb_axi_awcache;
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wire [2:0] sb_axi_awprot;
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wire [3:0] sb_axi_awqos;
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wire sb_axi_wvalid;
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wire sb_axi_wready;
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wire [63:0] sb_axi_wdata;
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wire [7:0] sb_axi_wstrb;
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wire sb_axi_wlast;
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wire sb_axi_bvalid;
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wire sb_axi_bready;
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wire [1:0] sb_axi_bresp;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_bid;
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// AXI Read Channels
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wire sb_axi_arvalid;
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wire sb_axi_arready;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_arid;
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wire [31:0] sb_axi_araddr;
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wire [3:0] sb_axi_arregion;
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wire [7:0] sb_axi_arlen;
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wire [2:0] sb_axi_arsize;
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wire [1:0] sb_axi_arburst;
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wire sb_axi_arlock;
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wire [3:0] sb_axi_arcache;
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wire [2:0] sb_axi_arprot;
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wire [3:0] sb_axi_arqos;
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wire sb_axi_rvalid;
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wire sb_axi_rready;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_rid;
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wire [63:0] sb_axi_rdata;
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wire [1:0] sb_axi_rresp;
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wire sb_axi_rlast;
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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wire dma_axi_awvalid;
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wire dma_axi_awready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;
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wire [31:0] dma_axi_awaddr;
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wire [2:0] dma_axi_awsize;
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wire [2:0] dma_axi_awprot;
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wire [7:0] dma_axi_awlen;
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wire [1:0] dma_axi_awburst;
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wire dma_axi_wvalid;
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wire dma_axi_wready;
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wire [63:0] dma_axi_wdata;
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wire [7:0] dma_axi_wstrb;
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wire dma_axi_wlast;
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wire dma_axi_bvalid;
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wire dma_axi_bready;
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wire [1:0] dma_axi_bresp;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;
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// AXI Read Channels
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wire dma_axi_arvalid;
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wire dma_axi_arready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;
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wire [31:0] dma_axi_araddr;
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wire [2:0] dma_axi_arsize;
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wire [2:0] dma_axi_arprot;
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wire [7:0] dma_axi_arlen;
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wire [1:0] dma_axi_arburst;
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wire dma_axi_rvalid;
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wire dma_axi_rready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;
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wire [63:0] dma_axi_rdata;
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wire [1:0] dma_axi_rresp;
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wire dma_axi_rlast;
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wire lmem_axi_arvalid;
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wire lmem_axi_arready;
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wire lmem_axi_rvalid;
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wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_rid;
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wire [1:0] lmem_axi_rresp;
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wire [63:0] lmem_axi_rdata;
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wire lmem_axi_rlast;
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wire lmem_axi_rready;
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wire lmem_axi_awvalid;
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wire lmem_axi_awready;
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wire lmem_axi_wvalid;
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wire lmem_axi_wready;
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wire [1:0] lmem_axi_bresp;
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wire lmem_axi_bvalid;
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wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_bid;
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wire lmem_axi_bready;
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initial begin
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jtag_id[31:28] = 4'b1;
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jtag_id[27:12] = '0;
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jtag_id[11:1] = 11'h45;
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reset_vector = 32'h0;
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nmi_vector = 32'hee000000;
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nmi_int = 0;
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$readmemh("program.hex", lmem.mem);
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$readmemh("program.hex", imem.mem);
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end
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quasar_wrapper rvtop (
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.reset (rst),
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.io_dbg_rst_l(dbg_rst),
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.clock (clk),
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.io_rst_vec (reset_vector[31:1]),
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.io_nmi_int (nmi_int),
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.io_nmi_vec (nmi_vector[31:1]),
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.io_jtag_id (jtag_id[31:1]),
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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.io_lsu_brg_aw_valid (lsu_axi_awvalid),
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.io_lsu_brg_aw_ready (lsu_axi_awready),
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.io_lsu_brg_aw_bits_id (lsu_axi_awid),
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.io_lsu_brg_aw_bits_addr (lsu_axi_awaddr),
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.io_lsu_brg_aw_bits_region(lsu_axi_awregion),
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.io_lsu_brg_aw_bits_len (lsu_axi_awlen),
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|
|
.io_lsu_brg_aw_bits_size (lsu_axi_awsize),
|
||
|
|
.io_lsu_brg_aw_bits_burst (lsu_axi_awburst),
|
||
|
|
.io_lsu_brg_aw_bits_lock (lsu_axi_awlock),
|
||
|
|
.io_lsu_brg_aw_bits_cache (lsu_axi_awcache),
|
||
|
|
.io_lsu_brg_aw_bits_prot (lsu_axi_awprot),
|
||
|
|
.io_lsu_brg_aw_bits_qos (lsu_axi_awqos),
|
||
|
|
|
||
|
|
.io_lsu_brg_w_valid (lsu_axi_wvalid),
|
||
|
|
.io_lsu_brg_w_ready (lsu_axi_wready),
|
||
|
|
.io_lsu_brg_w_bits_data(lsu_axi_wdata),
|
||
|
|
.io_lsu_brg_w_bits_strb(lsu_axi_wstrb),
|
||
|
|
.io_lsu_brg_w_bits_last(lsu_axi_wlast),
|
||
|
|
|
||
|
|
.io_lsu_brg_b_valid (lsu_axi_bvalid),
|
||
|
|
.io_lsu_brg_b_ready (lsu_axi_bready),
|
||
|
|
.io_lsu_brg_b_bits_resp(lsu_axi_bresp),
|
||
|
|
.io_lsu_brg_b_bits_id (lsu_axi_bid),
|
||
|
|
|
||
|
|
|
||
|
|
.io_lsu_brg_ar_valid (lsu_axi_arvalid),
|
||
|
|
.io_lsu_brg_ar_ready (lsu_axi_arready),
|
||
|
|
.io_lsu_brg_ar_bits_id (lsu_axi_arid),
|
||
|
|
.io_lsu_brg_ar_bits_addr (lsu_axi_araddr),
|
||
|
|
.io_lsu_brg_ar_bits_region(lsu_axi_arregion),
|
||
|
|
.io_lsu_brg_ar_bits_len (lsu_axi_arlen),
|
||
|
|
.io_lsu_brg_ar_bits_size (lsu_axi_arsize),
|
||
|
|
.io_lsu_brg_ar_bits_burst (lsu_axi_arburst),
|
||
|
|
.io_lsu_brg_ar_bits_lock (lsu_axi_arlock),
|
||
|
|
.io_lsu_brg_ar_bits_cache (lsu_axi_arcache),
|
||
|
|
.io_lsu_brg_ar_bits_prot (lsu_axi_arprot),
|
||
|
|
.io_lsu_brg_ar_bits_qos (lsu_axi_arqos),
|
||
|
|
|
||
|
|
.io_lsu_brg_r_valid (lsu_axi_rvalid),
|
||
|
|
.io_lsu_brg_r_ready (lsu_axi_rready),
|
||
|
|
.io_lsu_brg_r_bits_id (lsu_axi_rid),
|
||
|
|
.io_lsu_brg_r_bits_data(lsu_axi_rdata),
|
||
|
|
.io_lsu_brg_r_bits_resp(lsu_axi_rresp),
|
||
|
|
.io_lsu_brg_r_bits_last(lsu_axi_rlast),
|
||
|
|
|
||
|
|
//-------------------------- IFU AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.io_ifu_brg_aw_valid (ifu_axi_awvalid),
|
||
|
|
.io_ifu_brg_aw_ready (ifu_axi_awready),
|
||
|
|
.io_ifu_brg_aw_bits_id (ifu_axi_awid),
|
||
|
|
.io_ifu_brg_aw_bits_addr (ifu_axi_awaddr),
|
||
|
|
.io_ifu_brg_aw_bits_region(ifu_axi_awregion),
|
||
|
|
.io_ifu_brg_aw_bits_len (ifu_axi_awlen),
|
||
|
|
.io_ifu_brg_aw_bits_size (ifu_axi_awsize),
|
||
|
|
.io_ifu_brg_aw_bits_burst (ifu_axi_awburst),
|
||
|
|
.io_ifu_brg_aw_bits_lock (ifu_axi_awlock),
|
||
|
|
.io_ifu_brg_aw_bits_cache (ifu_axi_awcache),
|
||
|
|
.io_ifu_brg_aw_bits_prot (ifu_axi_awprot),
|
||
|
|
.io_ifu_brg_aw_bits_qos (ifu_axi_awqos),
|
||
|
|
|
||
|
|
.io_ifu_brg_w_valid (ifu_axi_wvalid),
|
||
|
|
.io_ifu_brg_w_ready (ifu_axi_wready),
|
||
|
|
.io_ifu_brg_w_bits_data(ifu_axi_wdata),
|
||
|
|
.io_ifu_brg_w_bits_strb(ifu_axi_wstrb),
|
||
|
|
.io_ifu_brg_w_bits_last(ifu_axi_wlast),
|
||
|
|
|
||
|
|
.io_ifu_brg_b_valid (ifu_axi_bvalid),
|
||
|
|
.io_ifu_brg_b_ready (ifu_axi_bready),
|
||
|
|
.io_ifu_brg_b_bits_resp(ifu_axi_bresp),
|
||
|
|
.io_ifu_brg_b_bits_id (ifu_axi_bid),
|
||
|
|
|
||
|
|
.io_ifu_brg_ar_valid (ifu_axi_arvalid),
|
||
|
|
.io_ifu_brg_ar_ready (ifu_axi_arready),
|
||
|
|
.io_ifu_brg_ar_bits_id (ifu_axi_arid),
|
||
|
|
.io_ifu_brg_ar_bits_addr (ifu_axi_araddr),
|
||
|
|
.io_ifu_brg_ar_bits_region(ifu_axi_arregion),
|
||
|
|
.io_ifu_brg_ar_bits_len (ifu_axi_arlen),
|
||
|
|
.io_ifu_brg_ar_bits_size (ifu_axi_arsize),
|
||
|
|
.io_ifu_brg_ar_bits_burst (ifu_axi_arburst),
|
||
|
|
.io_ifu_brg_ar_bits_lock (ifu_axi_arlock),
|
||
|
|
.io_ifu_brg_ar_bits_cache (ifu_axi_arcache),
|
||
|
|
.io_ifu_brg_ar_bits_prot (ifu_axi_arprot),
|
||
|
|
.io_ifu_brg_ar_bits_qos (ifu_axi_arqos),
|
||
|
|
|
||
|
|
.io_ifu_brg_r_valid (ifu_axi_rvalid),
|
||
|
|
.io_ifu_brg_r_ready (ifu_axi_rready),
|
||
|
|
.io_ifu_brg_r_bits_id (ifu_axi_rid),
|
||
|
|
.io_ifu_brg_r_bits_data(ifu_axi_rdata),
|
||
|
|
.io_ifu_brg_r_bits_resp(ifu_axi_rresp),
|
||
|
|
.io_ifu_brg_r_bits_last(ifu_axi_rlast),
|
||
|
|
|
||
|
|
//-------------------------- SB AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.io_sb_brg_aw_valid (sb_axi_awvalid),
|
||
|
|
.io_sb_brg_aw_ready (sb_axi_awready),
|
||
|
|
.io_sb_brg_aw_bits_id (sb_axi_awid),
|
||
|
|
.io_sb_brg_aw_bits_addr (sb_axi_awaddr),
|
||
|
|
.io_sb_brg_aw_bits_region(sb_axi_awregion),
|
||
|
|
.io_sb_brg_aw_bits_len (sb_axi_awlen),
|
||
|
|
.io_sb_brg_aw_bits_size (sb_axi_awsize),
|
||
|
|
.io_sb_brg_aw_bits_burst (sb_axi_awburst),
|
||
|
|
.io_sb_brg_aw_bits_lock (sb_axi_awlock),
|
||
|
|
.io_sb_brg_aw_bits_cache (sb_axi_awcache),
|
||
|
|
.io_sb_brg_aw_bits_prot (sb_axi_awprot),
|
||
|
|
.io_sb_brg_aw_bits_qos (sb_axi_awqos),
|
||
|
|
|
||
|
|
.io_sb_brg_w_valid (sb_axi_wvalid),
|
||
|
|
.io_sb_brg_w_ready (sb_axi_wready),
|
||
|
|
.io_sb_brg_w_bits_data(sb_axi_wdata),
|
||
|
|
.io_sb_brg_w_bits_strb(sb_axi_wstrb),
|
||
|
|
.io_sb_brg_w_bits_last(sb_axi_wlast),
|
||
|
|
|
||
|
|
.io_sb_brg_b_valid (sb_axi_bvalid),
|
||
|
|
.io_sb_brg_b_ready (sb_axi_bready),
|
||
|
|
.io_sb_brg_b_bits_resp(sb_axi_bresp),
|
||
|
|
.io_sb_brg_b_bits_id (sb_axi_bid),
|
||
|
|
|
||
|
|
|
||
|
|
.io_sb_brg_ar_valid (sb_axi_arvalid),
|
||
|
|
.io_sb_brg_ar_ready (sb_axi_arready),
|
||
|
|
.io_sb_brg_ar_bits_id (sb_axi_arid),
|
||
|
|
.io_sb_brg_ar_bits_addr (sb_axi_araddr),
|
||
|
|
.io_sb_brg_ar_bits_region(sb_axi_arregion),
|
||
|
|
.io_sb_brg_ar_bits_len (sb_axi_arlen),
|
||
|
|
.io_sb_brg_ar_bits_size (sb_axi_arsize),
|
||
|
|
.io_sb_brg_ar_bits_burst (sb_axi_arburst),
|
||
|
|
.io_sb_brg_ar_bits_lock (sb_axi_arlock),
|
||
|
|
.io_sb_brg_ar_bits_cache (sb_axi_arcache),
|
||
|
|
.io_sb_brg_ar_bits_prot (sb_axi_arprot),
|
||
|
|
.io_sb_brg_ar_bits_qos (sb_axi_arqos),
|
||
|
|
|
||
|
|
.io_sb_brg_r_valid (sb_axi_rvalid),
|
||
|
|
.io_sb_brg_r_ready (sb_axi_rready),
|
||
|
|
.io_sb_brg_r_bits_id (sb_axi_rid),
|
||
|
|
.io_sb_brg_r_bits_data(sb_axi_rdata),
|
||
|
|
.io_sb_brg_r_bits_resp(sb_axi_rresp),
|
||
|
|
.io_sb_brg_r_bits_last(sb_axi_rlast),
|
||
|
|
|
||
|
|
//-------------------------- DMA AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.io_dma_brg_aw_valid (dma_axi_awvalid),
|
||
|
|
.io_dma_brg_aw_ready (dma_axi_awready),
|
||
|
|
.io_dma_brg_aw_bits_id ('0),
|
||
|
|
.io_dma_brg_aw_bits_addr (lsu_axi_awaddr),
|
||
|
|
.io_dma_brg_aw_bits_size (lsu_axi_awsize),
|
||
|
|
.io_dma_brg_aw_bits_prot (lsu_axi_awprot),
|
||
|
|
.io_dma_brg_aw_bits_len (lsu_axi_awlen),
|
||
|
|
.io_dma_brg_aw_bits_burst (lsu_axi_awburst),
|
||
|
|
.io_dma_brg_aw_bits_region(lsu_axi_awregion),
|
||
|
|
.io_dma_brg_aw_bits_lock (lsu_axi_awlock),
|
||
|
|
.io_dma_brg_aw_bits_cache (lsu_axi_awcache),
|
||
|
|
.io_dma_brg_aw_bits_qos (lsu_axi_awqos),
|
||
|
|
|
||
|
|
.io_dma_brg_w_valid (dma_axi_wvalid),
|
||
|
|
.io_dma_brg_w_ready (dma_axi_wready),
|
||
|
|
.io_dma_brg_w_bits_data(lsu_axi_wdata),
|
||
|
|
.io_dma_brg_w_bits_strb(lsu_axi_wstrb),
|
||
|
|
.io_dma_brg_w_bits_last(lsu_axi_wlast),
|
||
|
|
|
||
|
|
.io_dma_brg_b_valid (dma_axi_bvalid),
|
||
|
|
.io_dma_brg_b_ready (dma_axi_bready),
|
||
|
|
.io_dma_brg_b_bits_resp(dma_axi_bresp),
|
||
|
|
.io_dma_brg_b_bits_id (),
|
||
|
|
|
||
|
|
.io_dma_brg_ar_valid (dma_axi_arvalid),
|
||
|
|
.io_dma_brg_ar_ready (dma_axi_arready),
|
||
|
|
.io_dma_brg_ar_bits_id ('0),
|
||
|
|
.io_dma_brg_ar_bits_addr (lsu_axi_araddr),
|
||
|
|
.io_dma_brg_ar_bits_size (lsu_axi_arsize),
|
||
|
|
.io_dma_brg_ar_bits_prot (lsu_axi_arprot),
|
||
|
|
.io_dma_brg_ar_bits_len (lsu_axi_arlen),
|
||
|
|
.io_dma_brg_ar_bits_burst (lsu_axi_arburst),
|
||
|
|
.io_dma_brg_ar_bits_region(lsu_axi_arregion),
|
||
|
|
.io_dma_brg_ar_bits_lock (lsu_axi_arlock),
|
||
|
|
.io_dma_brg_ar_bits_cache (lsu_axi_arcache),
|
||
|
|
.io_dma_brg_ar_bits_qos (lsu_axi_arqos),
|
||
|
|
|
||
|
|
.io_dma_brg_r_valid (dma_axi_rvalid),
|
||
|
|
.io_dma_brg_r_ready (dma_axi_rready),
|
||
|
|
.io_dma_brg_r_bits_id (),
|
||
|
|
.io_dma_brg_r_bits_data(dma_axi_rdata),
|
||
|
|
.io_dma_brg_r_bits_resp(dma_axi_rresp),
|
||
|
|
.io_dma_brg_r_bits_last(dma_axi_rlast),
|
||
|
|
|
||
|
|
.io_timer_int (1'b0),
|
||
|
|
.io_extintsrc_req('0),
|
||
|
|
|
||
|
|
.io_lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
|
||
|
|
.io_ifu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
|
||
|
|
.io_dbg_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB Debug master interface
|
||
|
|
.io_dma_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB slave interface
|
||
|
|
|
||
|
|
.io_rv_trace_pkt_rv_i_insn_ip (trace_rv_i_insn_ip),
|
||
|
|
.io_rv_trace_pkt_rv_i_address_ip (trace_rv_i_address_ip),
|
||
|
|
.io_rv_trace_pkt_rv_i_valid_ip (trace_rv_i_valid_ip),
|
||
|
|
.io_rv_trace_pkt_rv_i_exception_ip(trace_rv_i_exception_ip),
|
||
|
|
.io_rv_trace_pkt_rv_i_ecause_ip (trace_rv_i_ecause_ip),
|
||
|
|
.io_rv_trace_pkt_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
|
||
|
|
.io_rv_trace_pkt_rv_i_tval_ip (trace_rv_i_tval_ip),
|
||
|
|
|
||
|
|
.io_jtag_tck (jtag_tck),
|
||
|
|
.io_jtag_tms (jtag_tms),
|
||
|
|
.io_jtag_tdi (jtag_tdi),
|
||
|
|
.io_jtag_trst_n(jtag_trst_n),
|
||
|
|
.io_jtag_tdo (jtag_tdo),
|
||
|
|
|
||
|
|
.io_mpc_debug_halt_ack(mpc_debug_halt_ack),
|
||
|
|
.io_mpc_debug_halt_req(1'b0),
|
||
|
|
.io_mpc_debug_run_ack (mpc_debug_run_ack),
|
||
|
|
.io_mpc_debug_run_req (1'b1),
|
||
|
|
.io_mpc_reset_run_req (1'b1), // Start running after reset
|
||
|
|
.io_debug_brkpt_status(debug_brkpt_status),
|
||
|
|
|
||
|
|
.io_i_cpu_halt_req(1'b0), // Async halt req to CPU
|
||
|
|
.io_o_cpu_halt_ack(o_cpu_halt_ack), // core response to halt
|
||
|
|
.io_o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted
|
||
|
|
.io_i_cpu_run_req(1'b0), // Async restart req to CPU
|
||
|
|
.io_o_debug_mode_status(o_debug_mode_status),
|
||
|
|
.io_o_cpu_run_ack(o_cpu_run_ack), // Core response to run req
|
||
|
|
|
||
|
|
.io_dccm_ext_in_pkt_TEST1_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST1_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST1_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST1_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_RME_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_RME_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_RME_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_RME_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_RM_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_RM_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_RM_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_RM_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_LS_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_LS_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_LS_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_LS_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_DS_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_DS_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_DS_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_DS_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_SD_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_SD_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_SD_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_SD_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST_RNM_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST_RNM_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST_RNM_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_TEST_RNM_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC1_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC1_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC1_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC1_3('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC2_0('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC2_1('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC2_2('0),
|
||
|
|
.io_dccm_ext_in_pkt_BC2_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST1_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST1_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST1_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST1_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_RME_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_RME_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_RME_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_RME_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_RM_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_RM_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_RM_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_RM_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_LS_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_LS_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_LS_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_LS_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_DS_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_DS_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_DS_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_DS_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_SD_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_SD_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_SD_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_SD_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST_RNM_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST_RNM_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST_RNM_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_TEST_RNM_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC1_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC1_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC1_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC1_3('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC2_0('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC2_1('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC2_2('0),
|
||
|
|
.io_iccm_ext_in_pkt_BC2_3('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_TEST1_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_TEST1_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_RME_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_RME_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_RM_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_RM_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_LS_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_LS_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_DS_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_DS_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_SD_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_SD_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_TEST_RNM_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_TEST_RNM_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_BC1_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_BC1_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_BC2_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_0_BC2_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_TEST1_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_TEST1_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_RME_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_RME_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_RM_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_RM_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_LS_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_LS_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_DS_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_DS_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_SD_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_SD_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_TEST_RNM_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_TEST_RNM_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_BC1_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_BC1_1('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_BC2_0('0),
|
||
|
|
.io_ic_data_ext_in_pkt_1_BC2_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_TEST1_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_TEST1_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_RME_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_RME_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_RM_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_RM_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_LS_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_LS_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_DS_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_DS_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_SD_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_SD_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_TEST_RNM_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_TEST_RNM_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_BC1_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_BC1_1('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_BC2_0('0),
|
||
|
|
.io_ic_tag_ext_in_pkt_BC2_1('0),
|
||
|
|
|
||
|
|
.io_dec_tlu_perfcnt0(),
|
||
|
|
.io_dec_tlu_perfcnt1(),
|
||
|
|
.io_dec_tlu_perfcnt2(),
|
||
|
|
.io_dec_tlu_perfcnt3(),
|
||
|
|
|
||
|
|
.io_soft_int ('0),
|
||
|
|
.io_core_id ('0),
|
||
|
|
.io_scan_mode (1'b0), // To enable scan mode
|
||
|
|
.io_mbist_mode(1'b0) // to enable mbist
|
||
|
|
|
||
|
|
);
|
||
|
|
|
||
|
|
axi_slv #(
|
||
|
|
.TAGW(`RV_IFU_BUS_TAG)
|
||
|
|
) imem (
|
||
|
|
.aclk(clk),
|
||
|
|
.rst_l(rst),
|
||
|
|
.arvalid(ifu_axi_arvalid),
|
||
|
|
.arready(ifu_axi_arready),
|
||
|
|
.araddr(ifu_axi_araddr),
|
||
|
|
.arid(ifu_axi_arid),
|
||
|
|
.arlen(ifu_axi_arlen),
|
||
|
|
.arburst(ifu_axi_arburst),
|
||
|
|
.arsize(ifu_axi_arsize),
|
||
|
|
|
||
|
|
.rvalid(ifu_axi_rvalid),
|
||
|
|
.rready(ifu_axi_rready),
|
||
|
|
.rdata(ifu_axi_rdata),
|
||
|
|
.rresp(ifu_axi_rresp),
|
||
|
|
.rid(ifu_axi_rid),
|
||
|
|
.rlast(ifu_axi_rlast),
|
||
|
|
|
||
|
|
.awvalid(1'b0),
|
||
|
|
.awready(),
|
||
|
|
.awaddr('0),
|
||
|
|
.awid('0),
|
||
|
|
.awlen('0),
|
||
|
|
.awburst('0),
|
||
|
|
.awsize('0),
|
||
|
|
|
||
|
|
.wdata ('0),
|
||
|
|
.wstrb ('0),
|
||
|
|
.wvalid(1'b0),
|
||
|
|
.wready(),
|
||
|
|
|
||
|
|
.bvalid(),
|
||
|
|
.bready(1'b0),
|
||
|
|
.bresp(),
|
||
|
|
.bid()
|
||
|
|
);
|
||
|
|
|
||
|
|
defparam lmem.TAGW = `RV_LSU_BUS_TAG;
|
||
|
|
|
||
|
|
//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(
|
||
|
|
axi_slv lmem (
|
||
|
|
.aclk(clk),
|
||
|
|
.rst_l(rst),
|
||
|
|
.arvalid(lmem_axi_arvalid),
|
||
|
|
.arready(lmem_axi_arready),
|
||
|
|
.araddr(lsu_axi_araddr),
|
||
|
|
.arid(lsu_axi_arid),
|
||
|
|
.arlen(lsu_axi_arlen),
|
||
|
|
.arburst(lsu_axi_arburst),
|
||
|
|
.arsize(lsu_axi_arsize),
|
||
|
|
|
||
|
|
.rvalid(lmem_axi_rvalid),
|
||
|
|
.rready(lmem_axi_rready),
|
||
|
|
.rdata(lmem_axi_rdata),
|
||
|
|
.rresp(lmem_axi_rresp),
|
||
|
|
.rid(lmem_axi_rid),
|
||
|
|
.rlast(lmem_axi_rlast),
|
||
|
|
|
||
|
|
.awvalid(lmem_axi_awvalid),
|
||
|
|
.awready(lmem_axi_awready),
|
||
|
|
.awaddr(lsu_axi_awaddr),
|
||
|
|
.awid(lsu_axi_awid),
|
||
|
|
.awlen(lsu_axi_awlen),
|
||
|
|
.awburst(lsu_axi_awburst),
|
||
|
|
.awsize(lsu_axi_awsize),
|
||
|
|
|
||
|
|
.wdata (lsu_axi_wdata),
|
||
|
|
.wstrb (lsu_axi_wstrb),
|
||
|
|
.wvalid(lmem_axi_wvalid),
|
||
|
|
.wready(lmem_axi_wready),
|
||
|
|
|
||
|
|
.bvalid(lmem_axi_bvalid),
|
||
|
|
.bready(lmem_axi_bready),
|
||
|
|
.bresp(lmem_axi_bresp),
|
||
|
|
.bid(lmem_axi_bid)
|
||
|
|
);
|
||
|
|
|
||
|
|
axi_lsu_dma_bridge #(`RV_LSU_BUS_TAG, `RV_LSU_BUS_TAG) bridge (
|
||
|
|
.clk(clk),
|
||
|
|
.reset_l(rst),
|
||
|
|
|
||
|
|
.m_arvalid(lsu_axi_arvalid),
|
||
|
|
.m_arid(lsu_axi_arid),
|
||
|
|
.m_araddr(lsu_axi_araddr),
|
||
|
|
.m_arready(lsu_axi_arready),
|
||
|
|
|
||
|
|
.m_rvalid(lsu_axi_rvalid),
|
||
|
|
.m_rready(lsu_axi_rready),
|
||
|
|
.m_rdata(lsu_axi_rdata),
|
||
|
|
.m_rid(lsu_axi_rid),
|
||
|
|
.m_rresp(lsu_axi_rresp),
|
||
|
|
.m_rlast(lsu_axi_rlast),
|
||
|
|
|
||
|
|
.m_awvalid(lsu_axi_awvalid),
|
||
|
|
.m_awid(lsu_axi_awid),
|
||
|
|
.m_awaddr(lsu_axi_awaddr),
|
||
|
|
.m_awready(lsu_axi_awready),
|
||
|
|
|
||
|
|
.m_wvalid(lsu_axi_wvalid),
|
||
|
|
.m_wready(lsu_axi_wready),
|
||
|
|
|
||
|
|
.m_bresp(lsu_axi_bresp),
|
||
|
|
.m_bvalid(lsu_axi_bvalid),
|
||
|
|
.m_bid(lsu_axi_bid),
|
||
|
|
.m_bready(lsu_axi_bready),
|
||
|
|
|
||
|
|
.s0_arvalid(lmem_axi_arvalid),
|
||
|
|
.s0_arready(lmem_axi_arready),
|
||
|
|
|
||
|
|
.s0_rvalid(lmem_axi_rvalid),
|
||
|
|
.s0_rid(lmem_axi_rid),
|
||
|
|
.s0_rresp(lmem_axi_rresp),
|
||
|
|
.s0_rdata(lmem_axi_rdata),
|
||
|
|
.s0_rlast(lmem_axi_rlast),
|
||
|
|
.s0_rready(lmem_axi_rready),
|
||
|
|
|
||
|
|
.s0_awvalid(lmem_axi_awvalid),
|
||
|
|
.s0_awready(lmem_axi_awready),
|
||
|
|
|
||
|
|
.s0_wvalid(lmem_axi_wvalid),
|
||
|
|
.s0_wready(lmem_axi_wready),
|
||
|
|
.s0_bresp(lmem_axi_bresp),
|
||
|
|
.s0_bvalid(lmem_axi_bvalid),
|
||
|
|
.s0_bid(lmem_axi_bid),
|
||
|
|
.s0_bready(lmem_axi_bready),
|
||
|
|
|
||
|
|
|
||
|
|
.s1_arvalid(dma_axi_arvalid),
|
||
|
|
.s1_arready(dma_axi_arready),
|
||
|
|
|
||
|
|
.s1_rvalid(dma_axi_rvalid),
|
||
|
|
.s1_rresp (dma_axi_rresp),
|
||
|
|
.s1_rdata (dma_axi_rdata),
|
||
|
|
.s1_rlast (dma_axi_rlast),
|
||
|
|
.s1_rready(dma_axi_rready),
|
||
|
|
|
||
|
|
.s1_awvalid(dma_axi_awvalid),
|
||
|
|
.s1_awready(dma_axi_awready),
|
||
|
|
|
||
|
|
.s1_wvalid(dma_axi_wvalid),
|
||
|
|
.s1_wready(dma_axi_wready),
|
||
|
|
|
||
|
|
.s1_bresp (dma_axi_bresp),
|
||
|
|
.s1_bvalid(dma_axi_bvalid),
|
||
|
|
.s1_bready(dma_axi_bready)
|
||
|
|
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|