2019-06-04 22:57:48 +08:00
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: lsu interface with interface queue
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// Comments:
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//
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//********************************************************************************
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module lsu_bus_intf
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import swerv_types::*;
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(
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input logic clk,
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input logic rst_l,
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input logic scan_mode,
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input logic dec_tlu_non_blocking_disable, // disable non block
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input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing
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input logic dec_tlu_ld_miss_byp_wb_disable, // disable ld miss bypass of the write buffer
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input logic dec_tlu_sideeffect_posted_disable, // disable posted writes to sideeffect addr to the bus
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// various clocks needed for the bus reads and writes
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input logic lsu_c1_dc3_clk,
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input logic lsu_c1_dc4_clk,
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input logic lsu_c1_dc5_clk,
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input logic lsu_c2_dc3_clk,
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input logic lsu_c2_dc4_clk,
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input logic lsu_c2_dc5_clk,
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input logic lsu_freeze_c1_dc2_clk,
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input logic lsu_freeze_c1_dc3_clk,
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input logic lsu_freeze_c2_dc2_clk,
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input logic lsu_freeze_c2_dc3_clk,
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input logic lsu_bus_ibuf_c1_clk,
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input logic lsu_bus_obuf_c1_clk,
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input logic lsu_bus_buf_c1_clk,
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input logic lsu_free_c2_clk,
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input logic free_clk,
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input logic lsu_busm_clk,
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input logic lsu_busreq_dc2, // bus request is in dc2
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input lsu_pkt_t lsu_pkt_dc1, // lsu packet flowing down the pipe
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input lsu_pkt_t lsu_pkt_dc2, // lsu packet flowing down the pipe
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input lsu_pkt_t lsu_pkt_dc3, // lsu packet flowing down the pipe
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input lsu_pkt_t lsu_pkt_dc4, // lsu packet flowing down the pipe
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input lsu_pkt_t lsu_pkt_dc5, // lsu packet flowing down the pipe
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input logic [31:0] lsu_addr_dc1, // lsu address flowing down the pipe
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input logic [31:0] lsu_addr_dc2, // lsu address flowing down the pipe
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input logic [31:0] lsu_addr_dc3, // lsu address flowing down the pipe
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input logic [31:0] lsu_addr_dc4, // lsu address flowing down the pipe
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input logic [31:0] lsu_addr_dc5, // lsu address flowing down the pipe
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input logic [31:0] end_addr_dc1, // lsu address flowing down the pipe
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input logic [31:0] end_addr_dc2, // lsu address flowing down the pipe
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input logic [31:0] end_addr_dc3, // lsu address flowing down the pipe
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input logic [31:0] end_addr_dc4, // lsu address flowing down the pipe
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input logic [31:0] end_addr_dc5, // lsu address flowing down the pipe
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input logic addr_external_dc2, // lsu instruction going to external
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input logic addr_external_dc3, // lsu instruction going to external
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input logic addr_external_dc4, // lsu instruction going to external
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input logic addr_external_dc5, // lsu instruction going to external
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input logic [63:0] store_data_dc2, // store data flowing down the pipe
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input logic [63:0] store_data_dc3, // store data flowing down the pipe
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input logic [31:0] store_data_dc4, // store data flowing down the pipe
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input logic [31:0] store_data_dc5, // store data flowing down the pipe
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input logic lsu_commit_dc5, // lsu instruction in dc5 commits
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input logic is_sideeffects_dc2, // lsu attribute is side_effects
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input logic is_sideeffects_dc3, // lsu attribute is side_effects
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input logic flush_dc2_up, // flush
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input logic flush_dc3, // flush
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input logic flush_dc4, // flush
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input logic flush_dc5, // flush
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input logic dec_tlu_cancel_e4, // cancel the bus load in dc4 and reset the freeze
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output logic lsu_freeze_dc3, // load goes to external and asserts freeze
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output logic lsu_busreq_dc5, // bus request is in dc5
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output logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry
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output logic lsu_bus_buffer_full_any, // write buffer is full
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output logic lsu_bus_buffer_empty_any, // write buffer is empty
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output logic [31:0] bus_read_data_dc3, // the bus return data
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output logic ld_bus_error_dc3, // bus error in dc3
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output logic [31:0] ld_bus_error_addr_dc3, // address of the bus error
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output logic lsu_imprecise_error_load_any, // imprecise load bus error
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output logic lsu_imprecise_error_store_any, // imprecise store bus error
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output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error
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// Non-blocking loads
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input logic dec_nonblock_load_freeze_dc2,
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output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam
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output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load
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output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads
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output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // tag of the enrty which needs to be invalidated
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output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam
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output logic lsu_nonblock_load_data_error, // non block load has an error
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output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
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output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
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// PMU events
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output logic lsu_pmu_bus_trxn,
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output logic lsu_pmu_bus_misaligned,
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output logic lsu_pmu_bus_error,
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output logic lsu_pmu_bus_busy,
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// AXI Write Channels
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output logic lsu_axi_awvalid,
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input logic lsu_axi_awready,
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output logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid,
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output logic [31:0] lsu_axi_awaddr,
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output logic [3:0] lsu_axi_awregion,
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output logic [7:0] lsu_axi_awlen,
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output logic [2:0] lsu_axi_awsize,
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output logic [1:0] lsu_axi_awburst,
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output logic lsu_axi_awlock,
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output logic [3:0] lsu_axi_awcache,
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output logic [2:0] lsu_axi_awprot,
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output logic [3:0] lsu_axi_awqos,
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output logic lsu_axi_wvalid,
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input logic lsu_axi_wready,
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output logic [63:0] lsu_axi_wdata,
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output logic [7:0] lsu_axi_wstrb,
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output logic lsu_axi_wlast,
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input logic lsu_axi_bvalid,
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output logic lsu_axi_bready,
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input logic [1:0] lsu_axi_bresp,
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input logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid,
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// AXI Read Channels
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output logic lsu_axi_arvalid,
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input logic lsu_axi_arready,
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output logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid,
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output logic [31:0] lsu_axi_araddr,
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output logic [3:0] lsu_axi_arregion,
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output logic [7:0] lsu_axi_arlen,
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output logic [2:0] lsu_axi_arsize,
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output logic [1:0] lsu_axi_arburst,
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output logic lsu_axi_arlock,
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output logic [3:0] lsu_axi_arcache,
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output logic [2:0] lsu_axi_arprot,
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output logic [3:0] lsu_axi_arqos,
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input logic lsu_axi_rvalid,
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output logic lsu_axi_rready,
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input logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid,
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input logic [63:0] lsu_axi_rdata,
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input logic [1:0] lsu_axi_rresp,
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input logic lsu_axi_rlast,
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input logic lsu_bus_clk_en
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);
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`include "global.h"
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logic ld_freeze_dc3;
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logic lsu_bus_clk_en_q;
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logic ldst_dual_dc1, ldst_dual_dc2, ldst_dual_dc3, ldst_dual_dc4, ldst_dual_dc5;
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logic lsu_busreq_dc3, lsu_busreq_dc4;
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logic [3:0] ldst_byteen_dc2, ldst_byteen_dc3, ldst_byteen_dc4, ldst_byteen_dc5;
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logic [7:0] ldst_byteen_ext_dc2, ldst_byteen_ext_dc3, ldst_byteen_ext_dc4, ldst_byteen_ext_dc5;
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logic [3:0] ldst_byteen_hi_dc2, ldst_byteen_hi_dc3, ldst_byteen_hi_dc4, ldst_byteen_hi_dc5;
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logic [3:0] ldst_byteen_lo_dc2, ldst_byteen_lo_dc3, ldst_byteen_lo_dc4, ldst_byteen_lo_dc5;
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logic is_sideeffects_dc4, is_sideeffects_dc5;
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logic [63:0] store_data_ext_dc3, store_data_ext_dc4, store_data_ext_dc5;
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logic [31:0] store_data_hi_dc3, store_data_hi_dc4, store_data_hi_dc5;
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logic [31:0] store_data_lo_dc3, store_data_lo_dc4, store_data_lo_dc5;
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logic addr_match_dw_lo_dc5_dc4, addr_match_dw_lo_dc5_dc3, addr_match_dw_lo_dc5_dc2;
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logic addr_match_word_lo_dc5_dc4, addr_match_word_lo_dc5_dc3, addr_match_word_lo_dc5_dc2;
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logic no_word_merge_dc5, no_dword_merge_dc5;
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logic ld_addr_dc3hit_lo_lo, ld_addr_dc3hit_hi_lo, ld_addr_dc3hit_lo_hi, ld_addr_dc3hit_hi_hi;
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logic ld_addr_dc4hit_lo_lo, ld_addr_dc4hit_hi_lo, ld_addr_dc4hit_lo_hi, ld_addr_dc4hit_hi_hi;
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logic ld_addr_dc5hit_lo_lo, ld_addr_dc5hit_hi_lo, ld_addr_dc5hit_lo_hi, ld_addr_dc5hit_hi_hi;
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logic [3:0] ld_byte_dc3hit_lo_lo, ld_byte_dc3hit_hi_lo, ld_byte_dc3hit_lo_hi, ld_byte_dc3hit_hi_hi;
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logic [3:0] ld_byte_dc4hit_lo_lo, ld_byte_dc4hit_hi_lo, ld_byte_dc4hit_lo_hi, ld_byte_dc4hit_hi_hi;
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logic [3:0] ld_byte_dc5hit_lo_lo, ld_byte_dc5hit_hi_lo, ld_byte_dc5hit_lo_hi, ld_byte_dc5hit_hi_hi;
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logic [3:0] ld_byte_hit_lo, ld_byte_dc3hit_lo, ld_byte_dc4hit_lo, ld_byte_dc5hit_lo;
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logic [3:0] ld_byte_hit_hi, ld_byte_dc3hit_hi, ld_byte_dc4hit_hi, ld_byte_dc5hit_hi;
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logic [31:0] ld_fwddata_dc3pipe_lo, ld_fwddata_dc4pipe_lo, ld_fwddata_dc5pipe_lo;
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logic [31:0] ld_fwddata_dc3pipe_hi, ld_fwddata_dc4pipe_hi, ld_fwddata_dc5pipe_hi;
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logic [3:0] ld_byte_hit_buf_lo, ld_byte_hit_buf_hi;
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logic [31:0] ld_fwddata_buf_lo, ld_fwddata_buf_hi;
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logic ld_hit_rdbuf_hi, ld_hit_rdbuf_lo;
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logic [31:0] ld_fwddata_rdbuf_hi, ld_fwddata_rdbuf_lo;
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logic [63:0] ld_fwddata_lo, ld_fwddata_hi;
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logic [31:0] ld_fwddata_dc2, ld_fwddata_dc3;
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logic [31:0] ld_bus_data_dc3;
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logic ld_full_hit_hi_dc2, ld_full_hit_lo_dc2;
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logic ld_hit_dc2, ld_full_hit_dc2, ld_full_hit_dc3;
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logic is_aligned_dc5;
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logic [63:32] ld_fwddata_dc2_nc;
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logic lsu_write_buffer_empty_any;
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assign lsu_write_buffer_empty_any = 1'b1;
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assign ldst_byteen_dc2[3:0] = ({4{lsu_pkt_dc2.by}} & 4'b0001) |
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({4{lsu_pkt_dc2.half}} & 4'b0011) |
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({4{lsu_pkt_dc2.word}} & 4'b1111);
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assign ldst_dual_dc1 = (lsu_addr_dc1[2] != end_addr_dc1[2]);
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assign lsu_freeze_dc3 = ld_freeze_dc3 & ~(flush_dc4 | flush_dc5);
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// Determine if the packet is word aligned
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assign is_aligned_dc5 = (lsu_pkt_dc5.word & (lsu_addr_dc5[1:0] == 2'b0)) |
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(lsu_pkt_dc5.half & (lsu_addr_dc5[0] == 1'b0));
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// Read/Write Buffer
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lsu_bus_buffer bus_buffer (
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.*
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);
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// Logic to determine if dc5 store can be coalesced or not with younger stores. Bypass ibuf if cannot colaesced
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assign addr_match_dw_lo_dc5_dc4 = (lsu_addr_dc5[31:3] == lsu_addr_dc4[31:3]);
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assign addr_match_dw_lo_dc5_dc3 = (lsu_addr_dc5[31:3] == lsu_addr_dc3[31:3]);
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assign addr_match_dw_lo_dc5_dc2 = (lsu_addr_dc5[31:3] == lsu_addr_dc2[31:3]);
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assign addr_match_word_lo_dc5_dc4 = addr_match_dw_lo_dc5_dc4 & ~(lsu_addr_dc5[2]^lsu_addr_dc4[2]);
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assign addr_match_word_lo_dc5_dc3 = addr_match_dw_lo_dc5_dc3 & ~(lsu_addr_dc5[2]^lsu_addr_dc3[2]);
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assign addr_match_word_lo_dc5_dc2 = addr_match_dw_lo_dc5_dc2 & ~(lsu_addr_dc5[2]^lsu_addr_dc2[2]);
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assign no_word_merge_dc5 = lsu_busreq_dc5 & ~ldst_dual_dc5 &
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((lsu_busreq_dc4 & (lsu_pkt_dc4.load | ~addr_match_word_lo_dc5_dc4)) |
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(lsu_busreq_dc3 & ~lsu_busreq_dc4 & (lsu_pkt_dc3.load | ~addr_match_word_lo_dc5_dc3)) |
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(lsu_busreq_dc2 & ~lsu_busreq_dc3 & ~lsu_busreq_dc4 & (lsu_pkt_dc2.load | ~addr_match_word_lo_dc5_dc2)));
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assign no_dword_merge_dc5 = lsu_busreq_dc5 & ~ldst_dual_dc5 &
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((lsu_busreq_dc4 & (lsu_pkt_dc4.load | ~addr_match_dw_lo_dc5_dc4)) |
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(lsu_busreq_dc3 & ~lsu_busreq_dc4 & (lsu_pkt_dc3.load | ~addr_match_dw_lo_dc5_dc3)) |
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(lsu_busreq_dc2 & ~lsu_busreq_dc3 & ~lsu_busreq_dc4 & (lsu_pkt_dc2.load | ~addr_match_dw_lo_dc5_dc2)));
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// Create Hi/Lo signals
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assign ldst_byteen_ext_dc2[7:0] = {4'b0,ldst_byteen_dc2[3:0]} << lsu_addr_dc2[1:0];
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assign ldst_byteen_ext_dc3[7:0] = {4'b0,ldst_byteen_dc3[3:0]} << lsu_addr_dc3[1:0];
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assign ldst_byteen_ext_dc4[7:0] = {4'b0,ldst_byteen_dc4[3:0]} << lsu_addr_dc4[1:0];
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assign ldst_byteen_ext_dc5[7:0] = {4'b0,ldst_byteen_dc5[3:0]} << lsu_addr_dc5[1:0];
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assign store_data_ext_dc3[63:0] = {32'b0,store_data_dc3[31:0]} << {lsu_addr_dc3[1:0],3'b0};
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assign store_data_ext_dc4[63:0] = {32'b0,store_data_dc4[31:0]} << {lsu_addr_dc4[1:0],3'b0};
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assign store_data_ext_dc5[63:0] = {32'b0,store_data_dc5[31:0]} << {lsu_addr_dc5[1:0],3'b0};
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assign ldst_byteen_hi_dc2[3:0] = ldst_byteen_ext_dc2[7:4];
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assign ldst_byteen_lo_dc2[3:0] = ldst_byteen_ext_dc2[3:0];
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assign ldst_byteen_hi_dc3[3:0] = ldst_byteen_ext_dc3[7:4];
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assign ldst_byteen_lo_dc3[3:0] = ldst_byteen_ext_dc3[3:0];
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assign ldst_byteen_hi_dc4[3:0] = ldst_byteen_ext_dc4[7:4];
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assign ldst_byteen_lo_dc4[3:0] = ldst_byteen_ext_dc4[3:0];
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assign ldst_byteen_hi_dc5[3:0] = ldst_byteen_ext_dc5[7:4];
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assign ldst_byteen_lo_dc5[3:0] = ldst_byteen_ext_dc5[3:0];
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assign store_data_hi_dc3[31:0] = store_data_ext_dc3[63:32];
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assign store_data_lo_dc3[31:0] = store_data_ext_dc3[31:0];
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assign store_data_hi_dc4[31:0] = store_data_ext_dc4[63:32];
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assign store_data_lo_dc4[31:0] = store_data_ext_dc4[31:0];
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assign store_data_hi_dc5[31:0] = store_data_ext_dc5[63:32];
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assign store_data_lo_dc5[31:0] = store_data_ext_dc5[31:0];
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assign ld_addr_dc3hit_lo_lo = (lsu_addr_dc2[31:2] == lsu_addr_dc3[31:2]) & lsu_pkt_dc3.valid & lsu_pkt_dc3.store & lsu_busreq_dc2;
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assign ld_addr_dc3hit_lo_hi = (end_addr_dc2[31:2] == lsu_addr_dc3[31:2]) & lsu_pkt_dc3.valid & lsu_pkt_dc3.store & lsu_busreq_dc2;
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assign ld_addr_dc3hit_hi_lo = (lsu_addr_dc2[31:2] == end_addr_dc3[31:2]) & lsu_pkt_dc3.valid & lsu_pkt_dc3.store & lsu_busreq_dc2;
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assign ld_addr_dc3hit_hi_hi = (end_addr_dc2[31:2] == end_addr_dc3[31:2]) & lsu_pkt_dc3.valid & lsu_pkt_dc3.store & lsu_busreq_dc2;
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assign ld_addr_dc4hit_lo_lo = (lsu_addr_dc2[31:2] == lsu_addr_dc4[31:2]) & lsu_pkt_dc4.valid & lsu_pkt_dc4.store & lsu_busreq_dc2;
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assign ld_addr_dc4hit_lo_hi = (end_addr_dc2[31:2] == lsu_addr_dc4[31:2]) & lsu_pkt_dc4.valid & lsu_pkt_dc4.store & lsu_busreq_dc2;
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assign ld_addr_dc4hit_hi_lo = (lsu_addr_dc2[31:2] == end_addr_dc4[31:2]) & lsu_pkt_dc4.valid & lsu_pkt_dc4.store & lsu_busreq_dc2;
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assign ld_addr_dc4hit_hi_hi = (end_addr_dc2[31:2] == end_addr_dc4[31:2]) & lsu_pkt_dc4.valid & lsu_pkt_dc4.store & lsu_busreq_dc2;
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assign ld_addr_dc5hit_lo_lo = (lsu_addr_dc2[31:2] == lsu_addr_dc5[31:2]) & lsu_pkt_dc5.valid & lsu_pkt_dc5.store & lsu_busreq_dc2;
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assign ld_addr_dc5hit_lo_hi = (end_addr_dc2[31:2] == lsu_addr_dc5[31:2]) & lsu_pkt_dc5.valid & lsu_pkt_dc5.store & lsu_busreq_dc2;
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assign ld_addr_dc5hit_hi_lo = (lsu_addr_dc2[31:2] == end_addr_dc5[31:2]) & lsu_pkt_dc5.valid & lsu_pkt_dc5.store & lsu_busreq_dc2;
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assign ld_addr_dc5hit_hi_hi = (end_addr_dc2[31:2] == end_addr_dc5[31:2]) & lsu_pkt_dc5.valid & lsu_pkt_dc5.store & lsu_busreq_dc2;
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for (genvar i=0; i<4; i++) begin
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assign ld_byte_dc3hit_lo_lo[i] = ld_addr_dc3hit_lo_lo & ldst_byteen_lo_dc3[i] & ldst_byteen_lo_dc2[i];
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assign ld_byte_dc3hit_lo_hi[i] = ld_addr_dc3hit_lo_hi & ldst_byteen_lo_dc3[i] & ldst_byteen_hi_dc2[i];
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assign ld_byte_dc3hit_hi_lo[i] = ld_addr_dc3hit_hi_lo & ldst_byteen_hi_dc3[i] & ldst_byteen_lo_dc2[i];
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assign ld_byte_dc3hit_hi_hi[i] = ld_addr_dc3hit_hi_hi & ldst_byteen_hi_dc3[i] & ldst_byteen_hi_dc2[i];
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assign ld_byte_dc4hit_lo_lo[i] = ld_addr_dc4hit_lo_lo & ldst_byteen_lo_dc4[i] & ldst_byteen_lo_dc2[i];
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assign ld_byte_dc4hit_lo_hi[i] = ld_addr_dc4hit_lo_hi & ldst_byteen_lo_dc4[i] & ldst_byteen_hi_dc2[i];
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assign ld_byte_dc4hit_hi_lo[i] = ld_addr_dc4hit_hi_lo & ldst_byteen_hi_dc4[i] & ldst_byteen_lo_dc2[i];
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assign ld_byte_dc4hit_hi_hi[i] = ld_addr_dc4hit_hi_hi & ldst_byteen_hi_dc4[i] & ldst_byteen_hi_dc2[i];
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assign ld_byte_dc5hit_lo_lo[i] = ld_addr_dc5hit_lo_lo & ldst_byteen_lo_dc5[i] & ldst_byteen_lo_dc2[i];
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assign ld_byte_dc5hit_lo_hi[i] = ld_addr_dc5hit_lo_hi & ldst_byteen_lo_dc5[i] & ldst_byteen_hi_dc2[i];
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assign ld_byte_dc5hit_hi_lo[i] = ld_addr_dc5hit_hi_lo & ldst_byteen_hi_dc5[i] & ldst_byteen_lo_dc2[i];
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assign ld_byte_dc5hit_hi_hi[i] = ld_addr_dc5hit_hi_hi & ldst_byteen_hi_dc5[i] & ldst_byteen_hi_dc2[i];
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assign ld_byte_hit_lo[i] = ld_byte_dc3hit_lo_lo[i] | ld_byte_dc3hit_hi_lo[i] |
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ld_byte_dc4hit_lo_lo[i] | ld_byte_dc4hit_hi_lo[i] |
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ld_byte_dc5hit_lo_lo[i] | ld_byte_dc5hit_hi_lo[i] |
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ld_byte_hit_buf_lo[i];
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//ld_hit_rdbuf_lo;
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assign ld_byte_hit_hi[i] = ld_byte_dc3hit_lo_hi[i] | ld_byte_dc3hit_hi_hi[i] |
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ld_byte_dc4hit_lo_hi[i] | ld_byte_dc4hit_hi_hi[i] |
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ld_byte_dc5hit_lo_hi[i] | ld_byte_dc5hit_hi_hi[i] |
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ld_byte_hit_buf_hi[i];
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//ld_hit_rdbuf_hi;
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assign ld_byte_dc3hit_lo[i] = ld_byte_dc3hit_lo_lo[i] | ld_byte_dc3hit_hi_lo[i];
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assign ld_byte_dc4hit_lo[i] = ld_byte_dc4hit_lo_lo[i] | ld_byte_dc4hit_hi_lo[i];
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assign ld_byte_dc5hit_lo[i] = ld_byte_dc5hit_lo_lo[i] | ld_byte_dc5hit_hi_lo[i];
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assign ld_byte_dc3hit_hi[i] = ld_byte_dc3hit_lo_hi[i] | ld_byte_dc3hit_hi_hi[i];
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assign ld_byte_dc4hit_hi[i] = ld_byte_dc4hit_lo_hi[i] | ld_byte_dc4hit_hi_hi[i];
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assign ld_byte_dc5hit_hi[i] = ld_byte_dc5hit_lo_hi[i] | ld_byte_dc5hit_hi_hi[i];
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assign ld_fwddata_dc3pipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_dc3hit_lo_lo[i]}} & store_data_lo_dc3[(8*i)+7:(8*i)]) |
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({8{ld_byte_dc3hit_hi_lo[i]}} & store_data_hi_dc3[(8*i)+7:(8*i)]);
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assign ld_fwddata_dc4pipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_dc4hit_lo_lo[i]}} & store_data_lo_dc4[(8*i)+7:(8*i)]) |
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({8{ld_byte_dc4hit_hi_lo[i]}} & store_data_hi_dc4[(8*i)+7:(8*i)]);
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assign ld_fwddata_dc5pipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_dc5hit_lo_lo[i]}} & store_data_lo_dc5[(8*i)+7:(8*i)]) |
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({8{ld_byte_dc5hit_hi_lo[i]}} & store_data_hi_dc5[(8*i)+7:(8*i)]);
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assign ld_fwddata_dc3pipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_dc3hit_lo_hi[i]}} & store_data_lo_dc3[(8*i)+7:(8*i)]) |
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({8{ld_byte_dc3hit_hi_hi[i]}} & store_data_hi_dc3[(8*i)+7:(8*i)]);
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assign ld_fwddata_dc4pipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_dc4hit_lo_hi[i]}} & store_data_lo_dc4[(8*i)+7:(8*i)]) |
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({8{ld_byte_dc4hit_hi_hi[i]}} & store_data_hi_dc4[(8*i)+7:(8*i)]);
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assign ld_fwddata_dc5pipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_dc5hit_lo_hi[i]}} & store_data_lo_dc5[(8*i)+7:(8*i)]) |
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({8{ld_byte_dc5hit_hi_hi[i]}} & store_data_hi_dc5[(8*i)+7:(8*i)]);
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// Final muxing between dc3/dc4/dc5
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assign ld_fwddata_lo[(8*i)+7:(8*i)] = ld_byte_dc3hit_lo[i] ? ld_fwddata_dc3pipe_lo[(8*i)+7:(8*i)] :
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ld_byte_dc4hit_lo[i] ? ld_fwddata_dc4pipe_lo[(8*i)+7:(8*i)] :
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ld_byte_dc5hit_lo[i] ? ld_fwddata_dc5pipe_lo[(8*i)+7:(8*i)] :
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ld_fwddata_buf_lo[(8*i)+7:(8*i)];
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assign ld_fwddata_hi[(8*i)+7:(8*i)] = ld_byte_dc3hit_hi[i] ? ld_fwddata_dc3pipe_hi[(8*i)+7:(8*i)] :
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ld_byte_dc4hit_hi[i] ? ld_fwddata_dc4pipe_hi[(8*i)+7:(8*i)] :
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ld_byte_dc5hit_hi[i] ? ld_fwddata_dc5pipe_hi[(8*i)+7:(8*i)] :
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ld_fwddata_buf_hi[(8*i)+7:(8*i)];
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end
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always_comb begin
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ld_full_hit_lo_dc2 = 1'b1;
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ld_full_hit_hi_dc2 = 1'b1;
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for (int i=0; i<4; i++) begin
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ld_full_hit_lo_dc2 &= (ld_byte_hit_lo[i] | ~ldst_byteen_lo_dc2[i]);
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ld_full_hit_hi_dc2 &= (ld_byte_hit_hi[i] | ~ldst_byteen_hi_dc2[i]);
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end
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end
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// This will be high if atleast one byte hit the stores in pipe/write buffer (dc3/dc4/dc5/wrbuf)
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assign ld_hit_dc2 = (|ld_byte_hit_lo[3:0]) | (|ld_byte_hit_hi[3:0]);
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// This will be high if all the bytes of load hit the stores in pipe/write buffer (dc3/dc4/dc5/wrbuf)
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assign ld_full_hit_dc2 = ld_full_hit_lo_dc2 & ld_full_hit_hi_dc2 & lsu_busreq_dc2 & lsu_pkt_dc2.load & ~is_sideeffects_dc2;
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assign {ld_fwddata_dc2_nc[63:32], ld_fwddata_dc2[31:0]} = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_dc2[1:0]);
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assign bus_read_data_dc3[31:0] = ld_full_hit_dc3 ? ld_fwddata_dc3[31:0] : ld_bus_data_dc3[31:0];
|
2019-08-14 03:48:48 +08:00
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|
2019-06-04 22:57:48 +08:00
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|
// Fifo flops
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rvdff #(.WIDTH(1)) lsu_full_hit_dc3ff (.din(ld_full_hit_dc2), .dout(ld_full_hit_dc3), .clk(lsu_freeze_c2_dc3_clk), .*);
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rvdff #(.WIDTH(32)) lsu_fwddata_dc3ff (.din(ld_fwddata_dc2[31:0]), .dout(ld_fwddata_dc3[31:0]), .clk(lsu_c1_dc3_clk), .*);
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rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(free_clk), .*);
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rvdff #(.WIDTH(1)) ldst_dual_dc2ff (.din(ldst_dual_dc1), .dout(ldst_dual_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
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rvdff #(.WIDTH(1)) ldst_dual_dc3ff (.din(ldst_dual_dc2), .dout(ldst_dual_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
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rvdff #(.WIDTH(1)) ldst_dual_dc4ff (.din(ldst_dual_dc3), .dout(ldst_dual_dc4), .clk(lsu_c1_dc4_clk), .*);
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rvdff #(.WIDTH(1)) ldst_dual_dc5ff (.din(ldst_dual_dc4), .dout(ldst_dual_dc5), .clk(lsu_c1_dc5_clk), .*);
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rvdff #(.WIDTH(1)) is_sideeffects_dc4ff (.din(is_sideeffects_dc3), .dout(is_sideeffects_dc4), .clk(lsu_c1_dc4_clk), .*);
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rvdff #(.WIDTH(1)) is_sideeffects_dc5ff (.din(is_sideeffects_dc4), .dout(is_sideeffects_dc5), .clk(lsu_c1_dc5_clk), .*);
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rvdff #(4) lsu_byten_dc3ff (.*, .din(ldst_byteen_dc2[3:0]), .dout(ldst_byteen_dc3[3:0]), .clk(lsu_freeze_c1_dc3_clk));
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rvdff #(4) lsu_byten_dc4ff (.*, .din(ldst_byteen_dc3[3:0]), .dout(ldst_byteen_dc4[3:0]), .clk(lsu_c1_dc4_clk));
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rvdff #(4) lsu_byten_dc5ff (.*, .din(ldst_byteen_dc4[3:0]), .dout(ldst_byteen_dc5[3:0]), .clk(lsu_c1_dc5_clk));
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`ifdef ASSERT_ON
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// Assertion to check ld imprecise error comes with right address
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// property lsu_ld_imprecise_error_check;
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// @(posedge clk) disable iff (~rst_l) lsu_imprecise_error_load_any |-> (lsu_imprecise_error_addr_any[31:0] == ld_imprecise_bus_error_addr[31:0]);
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// endproperty
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// assert_ld_imprecise_error_check: assert property (lsu_ld_imprecise_error_check) else
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// $display("Wrong imprecise error address when lsu_imprecise_error_load_any asserted");
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// // Assertion to check st imprecise error comes with right address
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// property lsu_st_imprecise_error_check;
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// @(posedge clk) disable iff (~rst_l) lsu_imprecise_error_store_any |-> (lsu_imprecise_error_addr_any[31:0] == store_bus_error_addr[31:0]);
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// endproperty
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// assert_st_imprecise_error_check: assert property (lsu_st_imprecise_error_check) else
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// $display("Wrong imprecise error address when lsu_imprecise_error_store_any asserted");
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`endif
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endmodule // lsu_bus_intf
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